Revision History
- First Edition: March 1999
- Second Edition: February 2000
Library name change MDL110 into STD110
All characteristic values are updated with mass product line characteristics.
Add high density compiled memories to second edition. (chapter 5)
The name of previous compiled memories are changed for example: spsram into spsram_lp
power equations are changed. (chapter 1)
Updated PLL information
Updated wire-load model
STD110
0.25
m 2.5V CMOS Standard Cell Library
for Pure Logic Products
Data Book
Copyright
2003, 2000, 1999 by Samsung Electronics Co., Ltd.
All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior
written consent of the publisher. Samsung assumes no responsibility for any errors resulting from the use of the
information contained herein, nor does it convey any license under the patent rights of Samsung or others.
Samsung reserves the right to make changes in its products or product specification to improve function or design
at any time, without notice.
SEC and STD110 are trademarks of Samsung Electronics Co., Ltd. Verilog is a registered trademark of Cadence
Design Systems, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Mentor is a registered
trademark or Mentor Graphics Co. Synopsys is a registered trademark of Synopsys, Inc.
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SEC ASIC
iv
STD110
Introduction
This databook contains information about STD110 0.25
m 2.5V standard cell library for pure Logic products
developed by SEC (Samsung Electronics Corporation).
The "library" basically contains various kinds of internal and I/O cells and soft-macros which are used for
developing ASIC (Application Specific Integrated Circuit). It also includes a design kit helping designers to
work in a workstation platform, and all sorts of design environments needed for an automatic chip design.
There are six chapters in this databook:
Chapter 1
Introduction
Chapter 2
Electrical Characteristics
Chapter 3
Internal Macrocells
Chapter 4
Input/Output Cells
Chapter 5
Compiled Macrocells
Chapter 6
PLL
In this databook, each cell is followed by its AC electrical characteristics, and these characteristic values are
almost equal when the corresponding cell is operated in a real chip.
The purpose of this databook is to prevent any misuse or misapplication of STD110 cell library by providing
precise information about the cell list, electrical data, directions for use, and matters demanding special
attention.
If you want to get more information about Digital cores and Analog cores that are not included in this
databook, access the Samsung ASIC web site(http://www.samsung.com/Products/Semiconductor/ASIC) or
contact head office.
SEC ASIC
v
STD110
Contents
1
Introduction
1.1 Library Description ................................................................................................................1-1
1.2 Features ................................................................................................................................1-2
1.3 EDA Support .........................................................................................................................1-4
1.4 Product Family ......................................................................................................................1-4
1.4.1 Analog Core Cell.................................................................................................1-4
1.4.2 Internal Macrocells..............................................................................................1-12
1.4.3 Compiled Macrocells...........................................................................................1-12
1.4.4 Input/Output Cells ...............................................................................................1-13
1.5
Timings .................................................................................................................................1-16
1.6
Delay Model..........................................................................................................................1-22
1.7
Testability Design Methodology ............................................................................................1-24
1.8
Maximum Fanouts ................................................................................................................1-27
1.9
Packages Capability by Lead Count ....................................................................................1-34
1.10 Power Dissipation .................................................................................................................1-37
1.11 V
DD
/V
SS
Rules and Guidelines .............................................................................................1-40
1.12 Crystal Oscillator Considerations .........................................................................................1-46
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
3
Internal Macrocells
Overview .......................................................................................................................................3-1
Summary Tables ...........................................................................................................................3-2
Logic Cells
AD2DH/AD2/AD2D2/AD2D4 .........................................................................................................3-17
AD3DH/AD3/AD3D2/AD3D4 .........................................................................................................3-19
AD4DH/AD4/AD4D2/AD4D4 .........................................................................................................3-21
AD5/AD5D2/AD5D4 ......................................................................................................................3-24
ND2DH/ND2/ND2D2/ND2D4 ........................................................................................................3-27
ND3DH/ND3/ND3D2/ND3D4 ........................................................................................................3-29
ND4DH/ND4/ND4D2/ND4D2B/ND4D4 .........................................................................................3-32
ND5/ND5D2/ND5D4......................................................................................................................3-35
ND6/ND6D2/ND6D4......................................................................................................................3-38
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