LH532000B
FEATURES
262,144 words
8 bit organization
(Byte mode)
131,072 words
16 bit organization
(Word mode)
BYTE input pin selects bit configuration
Access times: 120/150 ns (MAX.)
Low-power consumption:
Operating: 275 mW (MAX.)
Standby: 550
W (MAX.)
Programmable OE/OE and OE
1
/OE
1
/DC
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
48-pin, 12
18 mm
2
TSOP (Type I)
16 word-wide pinout
DESCRIPTION
The LH532000B is a 2M-bit mask-programmable
ROM with two programmable memory organizations,
byte and word modes. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
CMOS 2M (256K
8/128K
16) MROM
532000B-1
TOP VIEW
1
2
3
4
7
8
A
2
A
5
48
37
36
35
34
33
30
27
A
7
A
6
5
6
A
3
A
4
32
31
OE
1
/OE
1
/DC
A
10
A
11
A
13
A
15
BYTE
GND
D
14
9
10
11
40
39
A
9
A
1
12
29
D
15
/A
-1
(LSB)
28
D
7
OE/OE
A
0
CE
A
12
40-PIN DIP
40-PIN SOP
13
14
15
16
17
18
19
20
24
21
26
25
23
22
D
13
D
5
D
12
D
4
D
2
D
10
D
9
GND
D
8
D
1
D
0
D
3
D
11
V
CC
A
8
A
14
A
16
D
6
Figure 1. Pin Connections for DIP and
SOP Packages
1
532000B-5
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15
/A
-1
A
9
13
36
35
A
8
48-PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE/OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
NC
NC
NC
OE
1
/OE
1
/DC
NOTE: Reverse bend available on request.
Figure 2. Pin Connections for TSOP Package
LH532000B
CMOS 2M MROM
2
NOTES:
1.
D
15
/A
1
pin becomes LSB address input (A
1
) when the bit configuration is set in byte mode,
and data output (D
15
) when in word mode. BYTE input pin selects bit configuration.
2.
The active levels of OE/OE and OE
1
/OE
1
/DC are mask-programmable.
Selecting DC allows the outputs to be active for both high and low levels applied to this pin.
It is recommended to apply either a HIGH or a LOW to the DC pin.
532000B-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
29
A
7
A
6
V
CC
A
4
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
SENSE AMPLIFIER
GND
A
5
A
13
ADDRESS BUFFER
A
0
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
A
15
TIMING
GENERATOR
A
16
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
A
-1
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
DATA SELECTOR/OUTPUT BUFFER
21
11
30
OE
BUFFER
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
31
OE
1
/OE
1
/DC
OE/OE
CE
BYTE
10
12
1
3
6
7
8
5
4
9
36
37
38
39
2
40
35
34
33
32
20
18
16
14
24
17
15
13
26
19
28
22
23
25
27
29
Figure 3. LH532000B Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
A
1
Address input (BYTE mode)
1
A
0
A
16
Address input
D
0
D
15
Data output
1
CE
Chip enable input
OE/OE
Output enable input
2
SIGNAL
PIN NAME
NOTE
OE
1
/OE
1
/DC
Output enable input or
Don't care
2
BYTE
Byte/word mode switch
V
CC
Power supply (+5 V)
GND
Ground
CMOS 2M MROM
LH532000B
3
TRUTH TABLE
CE
OE/OE
OE
1
/OE
1
BYTE
A
1
(D
15
)
DATA OUTPUT
ADDRESS INPUT
SUPPLY CURRENT
D
0
D
7
D
8
D
15
LSB
MSB
H
X
X
X
X
High-Z
High-Z
Standby (I
SB
)
L
L/H
X
X
X
High-Z
High-Z
Operating (I
CC
)
L
X
L/H
X
X
High-Z
High-Z
Operating (I
CC
)
L
H/L
H/L
H
Input
inhibit
D
0
D
7
D
8
D
15
A
0
A
16
Operating (I
CC
)
L
H/L
H/L
L
L
D
0
D
7
High-Z
A
1
A
16
Operating (I
CC
)
L
H/L
H/L
L
H
D
8
D
15
High-Z
A
1
A
16
Operating (I
CC
)
NOTE:
1.
X = H or L, High-Z = High-impedance.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
0.3 to +7.0
V
Input voltage
V
IN
0.3 to V
CC
+ 0.3
V
Output voltage
V
OUT
0.3 to V
CC
+ 0.3
V
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
65 to +150
C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input `Low' voltage
V
IL
0.3
0.8
V
Input `High' voltage
V
IH
2.2
V
CC
+ 0.3
V
Output `Low' voltage
V
OL
I
OL
= 2.0 mA
0.4
V
Output `High' voltage
V
OH
I
OH
= 400
A
2.4
V
Input leakage current
| I
LI
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= t
RC
(MIN.)
50
mA
2
I
CC2
t
RC
= 1
s
45
I
CC3
t
RC
= t
RC
(MIN.)
45
mA
3
I
CC4
t
RC
= 1
s
40
Standby current
I
SB1
CE = V
IH
3
mA
I
SB2
CE = V
CC
- 0.2 V
100
A
Input capacitance
C
IN
f = 1 MHz
T
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
OE/OE
1
= V
IL
,
CE/OE/OE
1
= V
IH
2.
V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3.
V
IN
= (V
CC
- 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
LH532000B
CMOS 2M MROM
4
AC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
120 ns
150 ns
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
120
150
ns
Address access time
t
AA
120
150
ns
Chip enable access time
t
ACE
120
150
ns
Output enable delay time
t
OE
55
70
ns
Output hold time
t
OH
5
10
ns
CE to output in High-Z
t
CHZ
55
70
ns
1
OE to output in High-Z
t
OHZ
55
70
ns
NOTE:
1.
This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.6 V to 2.4 V
Input rise/fall time
10 ns
Input reference level
1.5 V
Output reference level
0.8 V and 2.2 V
Output load condition
1TTL +100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
t
OE
t
AA
(D
0
- D
15
)
t
OHZ
t
CHZ
532000B-3
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE 1)
D
0
- D
7
OE/OE
1
OE/OE
1
(A
0
- A
16
)
A-
1
- A
16
1. Data becomes valid after t
AA
, t
ACE
, and t
OE
from address
input, chip enable or output enable, respectively have been met.
2. Applied to byte mode. Signals in parentheses apply to word mode.
NOTES:
(NOTE 1)
(NOTE 2)
(NOTE 2)
Figure 4. Timing Diagram
CMOS 2M MROM
LH532000B
5
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