LH5324500
FEATURES
3,145,728 words
8 bit organization
(Byte mode)
1,572,864 words
16 bit organization
(Word mode)
Access time: 150 ns (MAX.)
Power consumption:
Operating: 357.5 mW (MAX.)
Standby: 550
W (MAX.)
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Package: 44-pin, 600-mil SOP
DESCRIPTION
The LH5324500 is a 24M-bit mask-programmable
ROM organized as 3,145,728
8 bits (Byte mode) or
1,572,864
16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
5324500-1
TOP VIEW
2
3
4
5
8
9
A
2
A
5
39
38
37
36
35
34
31
28
A
7
A
6
6
7
A
3
A
4
33
32
A
10
A
11
A
13
A
15
BYTE
GND
D
14
10
11
12
41
40
A
9
A
1
13
30
D
15
/A
-1
(LSB)
29
D
7
OE
A
0
CE
A
12
44-PIN SOP
14
15
16
17
18
19
20
21
25
27
26
24
23
D
13
D
5
D
12
D
4
D
2
D
10
D
9
GND
D
8
D
1
D
0
D
3
D
11
V
CC
A
8
A
14
A
16
D
6
42
1
A
18
NC
22
44
43
A
17
A
19
A
20
Figure 1. Pin Connections for SOP Package
CMOS 24M (3M
8/1.5M
16) MROM
1
NOTE:
1.
The D
15
/A
1
pin becomes LSB address input (A
1
) when the BYTE pin is set to be LOW in byte mode, and data output (D
15
) when set to
be HIGH in word mode. When the address inputs become 'High' to both A
19
and A
20
, the data outputs become `Unspecified'
since the data does not exist in this address area.
5324500-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
31
38
39
40
41
5
8
9
10
A
7
A
6
V
CC
A
4
MEMORY
MATRIX
(3,145,728 x 8)
(1,572,864 x 16)
SENSE AMPLIFIER
4
GND
7
42
A
5
6
A
13
37
ADDRESS BUFFER
A
0
11
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
36
A
15
35
12
TIMING
GENERATOR
A
16
34
A
-1
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
DATA SELECTOR/OUTPUT BUFFER
23
32
OE
BUFFER
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
33
OE
CE
BYTE
22
20
18
16
26
19
17
15
21
30
24
25
27
29
31
14
A
17
3
A
19
43
28
A
18
2
13
A
20
44
Figure 2. LH5324500 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
A
1
A
20
Address input
1
D
0
D
15
Data output
1
BYTE
Byte/word mode switch
1
CE
Chip Enable input
SIGNAL
PIN NAME
NOTE
OE
Output Enable input
V
CC
Power supply (+5 V)
GND
Ground
NC
No connection
LH5324500
CMOS 24M MROM
2
TRUTH TABLE
CE
OE
BYTE
A
1
(D
15
)
DATA OUTPUT
ADDRESS INPUT
SUPPLY
CURRENT
D
0
D
7
D
8
D
15
LSB
MSB
H
X
X
X
High-Z
High-Z
Standby (I
SB
)
L
H
X
X
High-Z
High-Z
Operating (I
CC
)
L
L
H
D
0
D
7
D
8
D
15
A
0
A
20
Operating (I
CC
)
L
L
L
L
D
0
D
7
High-Z
A
1
A
20
Operating (I
CC
)
L
L
L
H
D
8
D
15
High-Z
A
1
A
20
Operating (I
CC
)
NOTE:
X = H or L; High-Z = High-impedance
The D
15
/A
1
pin becomes LSB address input (A
1
) when the BYTE pin is set to be LOW in byte mode, and data output (D
15
) when set to
be HIGH in word mode. When the address input at both A
19
and A
20
is HIGH level, the data outputs become high-impedance because
this data does not have data.
TRUTH TABLE WHEN BOTH A
20
ADN A
19
ARE HIGH
CE
OE
BYTE
A
1
(D
15
)
A
20
A
19
DATA OUTPUT
ADDRESS INPUT
SUPPLY
CURRENT
D
0
D
7
D
8
D
15
LSB
MSB
H
X
X
X
X
X
High-Z
High-Z
Standby (I
SB
)
L
X
H
H
H
High-Z
High-Z
A
0
A
20
Operating (I
CC
)
L
X
H
H
H
High-Z
High-Z
A
1
A
20
Operating (I
CC
)
NOTE:
X = H or L; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
0.3 to +7.0
V
Input voltage
V
IN
0.3 to V
CC
+ 0.3
V
Output voltage
V
OUT
0.3 to V
CC
+ 0.3
V
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
65 to +150
C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input `High' voltage
V
IH
2.2
V
CC
+ 0.3
V
Input `Low' voltage
V
IL
0.3
0.8
V
Output `High' voltage
V
OH
I
OH
= 400
A
2.4
V
Output `Low' voltage
V
OL
I
OL
= 2.0 mA
0.4
V
Input leakage current
| I
LI
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= 150 ns
65
mA
2
I
CC2
t
RC
= 1
s
55
Standby current
I
SB1
CE = V
IH
2
mA
I
SB2
CE = V
CC
0.2 V
100
A
Input capacitance
C
IN
f = 1 MHz
T
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
CE/OE = V
IH
2.
V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
CMOS 24M MROM
LH5324500
3
AC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
150
ns
Address access time
t
AA
150
ns
Chip enable access time
t
ACE
150
ns
Output enable delay time
t
OE
70
ns
Output hold time
t
OH
5
ns
Output floating time
t
CHZ
60
ns
1
t
OHZ
60
ns
t
AHZ
70
ns
NOTE:
1.
This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.6 V to 2.4 V
Input signal rise/fall time
10 ns
Input reference level
1.5 V
Output reference level
0.8 V and 2.2 V
Output load condition
1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
LH5324500
CMOS 24M MROM
4
t
OE
D
0
- D
7
t
OHZ
t
CHZ
t
RC
CE
t
OH
DATA VALID
t
ACE
t
AA
OE
A
-1
- A
20
NOTE: The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
,
have concluded.
(NOTE)
(NOTE)
(NOTE)
5324500-3
Figure 3. Byte Mode (BYTE = V
IL
)
t
OE
D
0
- D
15
t
OHZ
t
CHZ
t
RC
CE
t
OH
DATA VALID
t
ACE
t
AA
OE
A
0
- A
20
NOTE: The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
,
have concluded.
5324500-4
(NOTE)
(NOTE)
(NOTE)
Figure 4. Word Mode (BYTE = V
IH
)
CMOS 24M MROM
LH5324500
5
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