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301
DESCRIPTION...
The SP8481 Series are complete monolithic data acquisition systems, featuring 8-channel
multiplexer, internal reference and 12-bit sampling A/D converter in 32pin packages. Linearity
errors of
0.5 and
1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no
missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer
settling plus acquisition time is 1.9
s maximum; A/D conversion time is 8.1
s maximum.
CONTROL
LOGIC
ADD. LATCH
MULTIPLEXER
8BIT/4BIT NIBBLE
OUTPUT
CLOCK
REFERENCE
12-BIT A/D
CONVERTER
MUX DECODE
s
Complete Monolithic 8-Channel,
12-Bit DAS
s
100kHz Throughput
s
16-Bit Microprocessor Bus Interface
s
Latched MUX Address
s
All-channel Deselect
s
8/4-Bit Nibble Output
s
No Missing Codes to 12-Bits
s
32-Pin Packages
s
200mW Max Power Dissipation
* Formerly part of the SP410 Series.
SP8481 Series*
Monolithic, 12Bit Data Acquisition System
302
ABSOLUTE MAXIMUM RATINGS
V
CC
to Common Ground .............................................. 0V to +16.5V
V
LOGIC
to Common Ground ............................................... 0V to +7V
Analog Common to Digital Common Ground ............... -0.5V to +1V
Digital Inputs to Common Ground .................... -0.5V to V
LOGIC
+0.5V
Digital Outputs to Common Ground ................. -0.5V to V
LOGIC
+0.5V
Multiplexer Analog Inputs ...................................... -16.5V to +31.5V
Gain and Offset Adjustment ................................ -0.5V to V
CC
+0.5V
Analog Input Maximum Current ............................................. 25mA
Temperature with Bias Applied ............................. -55
C to +125
C
Storage Temperature ............................................ -65
C to +150
C
Lead Temperature, Soldering .................................... 300
C, 10sec
SPECIFICATIONS
(T
A
= 25
C and nominal supply voltages unless otherwise noted)
MIN.
TYP.
MAX.
UNIT
CONDITIONS
ANALOG INPUTS
Input Voltage Range
0 to +5
V
Multiplexer Inputs
8
Configuration
Single-ended
Input Impedance
ON Channel
10
9
Parallel with 30pF
OFF Channel
10
10
Parallel with 5pF
Input Bias Current
Per Channel
10
nA
25
C
250
nA
55
C to +125
C
Crosstalk
OFF to ON Channel
90
dB
10kHz, 0V to +5V
Pktopk
80
dB
50kHz, 0V to +5V
Pktopk
70
dB
100kHz, 0V to +5V
Pktopk
ACCURACY
Resolution
12
Bits
Linearity Error
K, B
0.5
LSB
J, A
1
LSB
Differential Non-Linearity
K, B
1
LSB
J, A
2
LSB
Offset Error
2
LSB
Adjustable to zero
Gain Error
0.3
%FSR
Adjustable to zero
No Missing Codes
K, B
Guaranteed
TRANSFER CHARACTERISTICS
Throughput Rate
100
kHz
MUX Settling/Acquisition
1.9
s
A/D Conversion
8.1
s
STABILITY
Linearity
0.5
2.5
ppm/
C
Offset
5
25
ppm/
C
Gain
10
50
ppm/
C
DIGITAL INPUTS
Capacitance
5
pF
Logic Levels
V
IH
+2.4
+5.5
V
V
IL
0.5
+0.8
V
I
IH
5
A
I
IL
5
A
303
SPECIFICATIONS
(continued)
(T
A
= 25
C and nominal supply voltages unless otherwise noted)
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DIGITAL OUTPUTS
Capacitance
5
pF
Logic Levels
V
OH
+2.4
V
I
OH
500
A
V
OL
+0.4
V
I
OL
1.6mA
Leakage Current
40
A
High impedance, data bits only
Data Output
Offset Binary
POWER REQUIREMENTS
V
LOGIC
+4.5
+5.5
V
I
LOGIC
0.8
2
mA
V
CC
+11.4
+16.5
V
I
CC
9
12
mA
Power Dissipation
140
200
mW
ENVIRONMENTAL
Operating Temperature
Commercial; J, K
0
+70
C
Industrial; A, B
40
+85
C
Storage Temperature
65
+150
C
304
PIN ASSIGNMENTS...
(Refer to Page 11 for package configurations and dimensions)
1
16
2
3
4
5
6
7
8
9 10 11 12 13 14 15
17
23 22 21 20 19 18
24
30 29 28 27 26 25
32 31
STATUS
DB11/DB3
DB10/DB2
DB9/DB1
DB8/DB0 (LSB)
DB7
DB6
DB5
DB4
MAEN
MA2
MA1
MA0
LATCH
DIG. GND.
V
LOGIC
A
0
R/C
CE
V
CC
OFFSET ADJ.
GAIN ADJ.
ANA. GND.
ANA. IN. CH0
ANA. IN. CH1
ANA. IN. CH2
ANA. IN. CH3
ANA. IN. CH4
ANA. IN. CH5
ANA. IN. CH6
ANA. IN. CH7
CONTROL
LOGIC
CLOCK
12-BIT ADC
8-CHANNEL
MULTIPLEXER
DECODE
REF
CS
Table 1. Multiplexer Truth Table
MULTIPLEXER TRUTH TABLE
LATCH
MAEN MA
2
MA
1
MA
0
OPERATION
H -> L
0
0
0
0
CH
O
Selected
H -> L
0
0
0
1
CH
1
Selected
H -> L
0
0
1
0
CH
2
Selected
H -> L
0
0
1
1
CH
3
Selected
H -> L
0
1
0
0
CH
4
Selected
H -> L
0
1
0
1
CH
5
Selected
H -> L
0
1
1
0
CH
6
Selected
H -> L
0
1
1
1
CH
7
Selected
H -> L
1
n
n
n
All Deselected
0
X
X
X
X
Prev. Ch. n Held
1
X
X
X
X
Prev. Ch. n Held
PIN FUNCTION...
R/C -- Read/Convert -- Initiates conversion on
the Hi-to-low transition; logic low disconnects
data bus; logic high initiates read
CS -- Chip Select -- Logic high disconnects
data bus; logic low allows conversion or reading
of data
CE -- Chip Enable -- Logic low disables read or
convert; logic high enables read or convert
A
0
-- Device Address -- Logic low enables 8
MSB read; logic high enables 4 LSB read
MA
0
, MA
1
, MA
2
-- MUX Address 0, 1 & 2 --
Selects analog input channels CH
0
through CH
7
LATCH -- MUX Address Latch -- Logic high
to low transition captures MUX address on MUX
address lines
MAEN -- MUX Enable -- Logic low allows
normal MUX address; logic high deselects CH
O
through CH
7
DB
0
through DB
11
-- Data Outputs -- Logic
high is binary true; logic low binary false
Table 2. Control Truth Table
CONTROL TRUTH TABLE
CE
CS
A
O
R/C
OPERATION
0
X
X
X
None
X
1
X
X
None
L->H
0
0
X
Start Conversion
1
H ->L
0
X
Start Conversion
1
0
H ->L
X
Start Conversion
1
0
1
0
Enable 8 MSBs
1
0
1
1
Enable 4 LSBs
305
FEATURES...
The SP8481 Series are complete data acquisi-
tion systems, featuring 8-channel multiplexer,
internal reference and 12-bit sampling A/D con-
verter implemented as a single monolithic IC.
The analog multiplexer accepts 0V to +5V uni-
polar full scale inputs. Output data is formatted
as an 8-bit/4-bit nibble.
Linearity errors of
0.5 and
1.0 LSB, and
Differential Non-linearity to 12-bits is guaran-
teed, with no missing codes over temperature.
Channel-to-channel crosstalk is typically -85dB.
Multiplexer settling plus acquisition time is 1.9
s
maximum; A/D conversion time is 8.1
s maxi-
mum.
Versions of the SP8481 Series are available in
32-pin plastic DIP or SOIC packages. Operating
temperature ranges are 0
C to +70
C commer-
cial and -40
C to +85
C industrial.
CIRCUIT OPERATION...
The SP8481 is a complete 8-channel data acqui-
sition system (DAS), with on-board multiplexer,
voltage reference, sampleandhold, clock and
tristate outputs. The digital control architecture
is very similar to the industry-standard 574-type
A/D, and uses identical control lines and digital
states.
The multiplexer for the SP8481 is identical in
operation to many discrete devices available
today, except that it has been integrated into the
single-chip DAS. The appropriate channel is
selected using the MUX address lines MA
0
,
MA
1
, and MA
2
per the truth table. The selected
analog input is fed through to the ADC. The
input impedance into any MUX channel will be
on the order to 10
9
ohms, since it is connected to
the integral sampling structure of the capacitor
DAC. Crosstalk is kept to -85dB at 0V to 5V
p-p
over an input frequency range of 10kHz to 50kHz.
When the control section of the SP8481 initiates
a conversion command the internal clock is
enabled, and the successive approximation reg-
ister (SAR) is reset to all zeros. Once the conver-
sion has been started it cannot be stopped or
restarted. Data is not available at the output
buffers until the conversion has been completed.
The SAR, timed by the clock, sequences through
the conversion cycle and returns an endof
convert flag to the control section of the ADC.
The clock is then disabled by the control section,
which puts the STATUS output line low. The
control section is enabled to allow the data to be
read by external command (R/C).
Multiplexer Control and Inputs
On the SP8481 the multiplexer inputs are latched
with LATCH. The address line latches MA
0
,
MA
1
and MA
2
select the appropriate analog
input channel. When low, the LATCH line re-
tains the last MUX address data, and therefore
the previously addressed MUX channel. All
channels may be deselected by bringing the
MAEN control line to a logic "1". When this
control function is used, the analog input will be
connected to pin 8 or analog ground.
Since the MUX address latches are controlled by
the LATCH and MAEN control lines, MUX
channel select data need not be held by the bus
for any minimum period after the conversion has
been initiated. However it is advisable that the
MUX not be changed at all during the full 10
s
conversion time due to capacitive coupling ef-
fects of digital edges through the silicon.
The SP8481 multiplexer inputs have been de-
signed to allow substantial overvoltage condi-
tions to occur without any damage. The inputs
are diode-clamped and further protected with a
200
series resistor. As a result, momentary (10
seconds) input voltages can be as low as -16.5V
or as high as +31.5V with no change or degrada-
tion in multiplexer performance or crosstalk.
This feature allows the output voltage of an
externally connected op amp to swing to
15V
supply levels with no multiplexer damage. Com-
plicated power-up sequencing is not required to
protect the SP8481. The multiplexer inputs may
be damaged, however, if the inputs are allowed
to either source or sink greater than 100mA.
Initiating a Conversion
The SP8481 was designed to require a minimum
of control to perform a 12-bit conversion. The
control input used is R/C which tri-states the
306
SP8481
GAIN ADJUST
125K
+15V
10K
0.3% Trim Range
5
19K
Center pot
for zero
correction
SP8481
OFFSET ADJUST
100K
+15V
5K
1.5mV to +3mV
4
Figure 1. Offset Adjust
Figure 2. Gain Adjust
outputs when high and starts the conversion
when low. CS and CE may also be used with
R/C to initiate a conversion. The last of the three
inputs to reach the correct state starts the conver-
sion, therefore one, two or all three may be
dynamically controlled. The nominal delay from
all three is the same and they may change state
simultaneously. In order to ensure that a particu-
lar input controls the conversion the other two
should be set up at least 50ns earlier. The
STATUS line indicates when a conversion is in
process and when it is complete. The A
0
input is
used to configure the output data.
The conversion cycle is started when R/C is
brought low and must be held low for a minimum
of 50ns. The R/C signal will also put the output
latches in a tri-state mode when low. Approxi-
mately 200ns after R/C is low, STATUS will
change from low to high. This output signal will
stay high while the SP8481 is performing a
conversion. Valid data will be latched to the
output bus, through internal control, 500ns prior
to the STATUS line transitioning from a high to
low.
Reading the Data
The output data buffers will remain in a high
impedance state until the following four condi-
tions are met: R/C is HIGH, STATUS is LOW,
CE is HIGH and CS is LOW. The data lines
become active in response to the four conditions
and will latch data according to the conditions of
A
0
line. Please refer to Figure 5 for the appropri-
ate timing. All conditions must be met at least
50ns prior to reading the data to allow sufficient
time for the output latches to come out of the high
impedance state. A
0
is used to access the data.
The first 8 MSBs will be on pins 26 through 19,
with pin 26 being the MSB. The remaining 4
LSBs will be on pins 23 through 26 with pin 23
being the LSB. When A
0
is switched from one
state to the next, there is a 50ns output latch
propagation delay between the MSBs and LSBs
being present on the output pins.
CALIBRATION
The calibration procedure for the SP8481 con-
sists of adjusting the most negative input voltage
(0V) to the ideal output code for offset adjust-
ment, and then adjusting the most positive input
voltage (5.0V) to its ideal output code for gain
adjustment.
Offset Adjustment
The offset adjustment must be completed first.
Please refer to Figure 1. Apply an input voltage
of 0.5LSB or 610
V to any multiplexer input.
Adjust the offset potentiometer so that the output
code fluctuates evenly between 000...000 and
000...001. It is only necessary to observe the
lower eight LSB's during this procedure.
Gain Adjustment
With the offset adjusted, the gain error can now
be trimmed to zero. The ideal input voltage
corresponding to 1.5 LSB's below the nominal
full scale input value, or +4.988V, is applied to
any multiplexer input. The gain potentiometer is
adjusted so that the output code alternates evenly
between 111...111 and 111...110. Again, only
the lower eight LSB's need be observed during
this procedure. With the above adjustment made,
the converter is now calibrated.
307
LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS
V
CC
= +15V; V
LOGIC
= +5V; T
A
= 25
C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HRL
Low R/C Pulse Width
50
ns
t
DS
Status Delay from R/C
200
ns
t
HDR
Data Valid after R/C
25
ns
t
HS
Status Delay after Data Valid
500
ns
t
MDS
MUX Data Setup
50
ns
t
MDH
MUX Data Valid
3
10
s
R/C
STATUS
DB
11
- DB
0
t
HRL
t
C
DATA VALID
DATA VALID
t
MDH
t
DS
t
HDR
t
HS
MA
0
- MA
2
t
MDS
LATCH
Figure 3. Low Pulse for R/C Timing
308
CONVERT MODE DYNAMIC CHARACTERISTICS
V
CC
= +15V; V
LOGIC
= +5V; T
A
= 25
C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HEC
CE Pulse Width
50
ns
t
SSC
CS to CE Setup
50
ns
t
HSC
CS Low During CE High
50
ns
t
SRC
R/C to CE Setup
50
ns
t
HRC
R/C Low during CE High
50
ns
t
SAC
A
0
to CE Setup
0
ns
t
HAC
A
0
Valid During CE High
50
ns
t
DSC
Status Delay from CE
200
ns
t
C
Conversion Time
10
s
R/C
STATUS
DB
11
- DB
0
t
C
CE
t
SRC
t
HEC
HIGH IMPEDANCE
t
HRC
t
DSC
CS
t
SSC
t
HSC
A
0
t
SAC
t
HAC
Figure 4. Convert Mode Timing
309
READ MODE DYNAMIC CHARACTERISTICS
V
CC
= +15V; V
LOGIC
= +5V; T
A
= 25
C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HRS
CS Valid After CE Low
0
0
ns
t
SRR
R/C to CE Setup
50
0
ns
t
HRR
R/C High After CE Low
0
50
ns
t
SAR
A
0
to CE Setup
50
ns
t
HAR
A
0
Valid After CE Low
50
ns
Data Valid After CE Low
20
ns
t
DD
Access Time from CE
150
ns
t
HL
Output Float Delay
150
ns
R/C
STATUS
DB
11
- DB
0
CS
t
SRR
HIGH IMPEDANCE
t
HRR
DATA VALID
t
DD
t
HD
t
HL
A
0
t
SAR
t
HAR
CE
t
HRS
t
HS
Figure 5. Read Mode Timing
310
Figure 10. FFT; 48kHz, 1V (14dB) Input; F
S
=100kHz
Figure 6. FFT; 6kHz, 5V (0dB) Full Scale Input; F
S
=100kHz
Figure 9. FFT; 48kHz, 5V (0dB) Full Scale Input; F
S
=100kHz
Figure 8. FFT; 24kHz, 5V (0dB) Full Scale Input; F
S
=100kHz
Figure 7. FFT; 12kHz, 5V (0dB) Full Scale Input; F
S
=100kHz
311
ORDERING INFORMATION
12-Bit Data Acquisition System, Latched Multiplexer Address,
8-Bit/4-Bit Data Output:
Commercial (0
C to +70
C):
Integral NonLinearity
Package
SP8481JP ............................................................................
1.0LSB INL ....................................................................... 32pin, 0.6" Plastic DIP
SP8481KP ...........................................................................
0.5LSB INL ....................................................................... 32pin, 0.6" Plastic DIP
SP8481JS ............................................................................
1.0LSB INL ................................................................................ 32pin, 0.3" SOIC
SP8481KS ...........................................................................
0.5LSB INL ................................................................................ 32pin, 0.3" SOIC
Industrial (-40
C to +85
C):
Integral NonLinearity
Package
SP8481AP ...........................................................................
1.0LSB INL ....................................................................... 32pin, 0.6" Plastic DIP
SP8481BP ...........................................................................
0.5LSB INL ....................................................................... 32pin, 0.6" Plastic DIP
SP8481AS ...........................................................................
1.0LSB INL ................................................................................ 32pin, 0.3" SOIC
SP8481BS ...........................................................................
0.5LSB INL ................................................................................ 32pin, 0.3" SOIC
312
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