ST
Sitronix
ST8024
PRELIMINARY
240 Output LCD Common/Segment driver IC
Notice: This is not a final specification. Some parameters are subject to change
V1.0 1/26
2003-07-02
1. DESCRIPTION
The ST8024 is a 240-output segment/common driver
IC suitable for driving large/medium scale dot matrix
LCD panels, and is used in personal computers/work
stations. Through the use of SST (Super Slim TCP)
technology, it is ideal for substantially decreasing the
size of the frame section of the LCD module. The
ST8024 is good both as a segment driver and a
common driver, and it can create a low power
consuming, high-resolution LCD.
2. FEATURES
Number of LCD drive outputs: 240
Supply voltage for LCD drive: +15.0 to +42.0 V
Supply voltage for the logic system: +2.5 to +5.5 V
Low power consumption
Low output impedance
Package: 269-pin TCP (Tape Carrier Package)
(Segment mode)
Shift clock frequency
- 20 MHz (MAX.): V
DD
= +5.0 0.5 V
- 15 MHz (MAX.): V
DD
= +3.0 to + 4.5 V
- 12 MHz (MAX.): V
DD
= +2.5 to + 3.0 V
Adopts a data bus system
4-bit/8-bit parallel input modes are selectable with a
mode (MD) pin
Automatic transfer function of an enable signal
Automatic counting function which, in the chip
selection mode, causes the internal clock to be
stopped by automatically counting 240 bits of input
data
Line latch circuits are reset when DISPOFF active
(Common mode)
Shift clock frequency: 4 MHz (MAX.)
Built-in 240-bit bi-directional shift register (divisible
into 120 bits x 2)
Available in a single mode (240-bit shift register) or in
a dual mode (120-bit shift register x 2)
Y
1
->Y
240
Single mode
Y
240
->Y
1
Single mode
Y
1
->Y
l20
, Y
121
->Y
240
Dual mode
Y
240
->Y
121
, Y
l20
->Y
1
Dual mode
The above 4 shift directions are pin-selectable
Shift register circuits are reset when DISPOFF active
3. PIN CONNECTIONS
1
240
241
269
Y
1
Y
238
Y
239
Y
240
Y
3
Y
2
V
0R
V
0L
EIO
1
LP
DISPOFF
XCK
DI
0
EIO
2
SC
V
DD
V
43L
V
12L
DI
1
DI
7
DI
6
DI
5
DI
4
DI
3
DI
2
FR
V
SS
V
5R
V
43R
V
12R
TEST
2
TEST
1
L/R
MD
V
5L
269-PIN TCP
CHIP SURF
ACE
Sitronix ST8024
V1.0 2/26
2003-07-02
4. PIN DESCRIPTION (TCP)
PIN NO.
SYMBOL
I/O
DESCRIPTION
1 ~ 240
Y
1
-Y
240
0 LCD drive output
241, 269
V
OL
, V
OR
- Power supply for LCD drive
242, 268
V
12L
, V
12R
- Power supply for LCD drive
243, 267
V
43L
, V
43R
- Power supply for LCD drive
244, 266
V
5L
, V
5R
- Power supply for LCD drive
245 V
DD
- Power supply for logic system (+2.5 to +5.5 V)
246
S/C
I Segment mode/common mode selection
247, 259
EIO
2
, EIO
1
I/O
Input/output for chip selection at segment mode
Shift data input/output for shift register at common mode
248 ~ 254
DI
0
-DI
6
I Display data input at segment mode
255 DI
7
I Display data input at segment mode/Dual mode data input at common mode
256
XCK
I Clock input for taking display data at segment mode
257
/DISPOFF
I Control input for output of non-select level
258 LP
I Latch pulse input for display data at segment mode/
Shift clock input for shift register at common mode
260
FR
I AC-converting signal input for LCD drive waveform
261 L/R
I Input for selecting the reading direction of display data at segment mode/
Input for selecting the shift direction of shift register at common mode
262
MD
I Mode selection input
263 TEST
1
I Test mode selection pins
During normal operation, fix to V
SS
level "L".
265 V
SS
-
Ground
(0
V)
5. BLOCK DIAGRAM
240-BIT 4-LEVEL DRIVER
240-BIT LEVEL SHIFTER
240-BIT LINE LATCH/SHIFT REGISTER
DATA CONTROL
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
TEST
CIRCUIT
CONTROL
LOGIC
ACTIVE
CONTROL
LEVEL
SHIFTER
8 BIT
DATA
LATCH
248
249
250
251
255
254
253
252
260
257
259
247
258
256
261
262
246
269
268
267
266
1
2
239
240
244
243
242
241
265
245
263
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
TEST
1
V
DD
V
SS
V
5L
V
43L
V
12L
V
0L
Y
240
Y
239
Y
2
Y
1
V
5R
V
43R
V
12R
V
0R
FR
DISPOFF
EIO
1
EIO
2
LP
XCK
L/R
MD
S/C
8
16
16
16
240
240
BLANK
Sitronix ST8024
V1.0 3/26
2003-07-02
6. FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK FUNCTION
Active Control
In case of segment mode, controls the selection or non-selection of the chip.
Following an LP signal input, and after the chip selection signal is input, a selection signal is
generated internally until 240 bits of data have been read in.
Once data input has been completed, a selection signal for cascade connection is output, and
the chip is non-selected.
In case of common mode, controls the input/output data of bi-directional pins.
SP Conversion
& Data Control
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input
mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode
in latch circuit; after that they are put on the internal data bus 8 bits at a time.
Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic. For every 16 bits of data read in,
the selection signal shifts one bit based on the state of the control circuit.
Data Latch
In case of segment mode, latches the data on the data bus. The latch state of each LCD
drive output pin is controlled by the control logic and the data latch control; 240 bits of data are
read in 30 sets of 8 bits.
Line Latch/
Shift Register
In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched at the falling edge of the LP signal, and are output to the level shifter
block. In case of common mode, shifts data from the data input pin at the falling edge of the LP
signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the
driver block.
4-Level Driver
Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4
levels (V
0
, V
12
, V
43
or V
5
) based on the S/C, FR and /DISPOFF signals.
Control Logic
Controls the operation of each block. In case of segment mode, when an LP signal has been
input, all blocks are reset and the control logic waits for the selection signal output from the
active control block. Once the selection signal has been output, operation of the data latch and
data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. In
case of common mode, controls the direction of data shift.
Test Circuit
The circuit for testing. During normal operation, it isn't activated.
Sitronix ST8024
V1.0 4/26
2003-07-02
INPUT/OUTPUT CIRCUITS
I
V
DD
To Internal Circuit
Vss (0V)
Applicable Pins
L/R , S/C , DI
6
~DI
0
,
DISPOFF , LP , FR , MD
Fig. 1 Input Circuit (1)
I
V
DD
To Internal Circuit
Applicable Pins
DI
7
, XCK
Vss (0V)
Vss (0V)
Control Signal
Fig. 2 Input Circuit (2)
I
V
DD
To Internal Circuit
Applicable Pins
TEST
1
, TEST
2
Vss (0V)
Vss (0V)
V
DD
Fig. 3 Input Circuit (3)
Sitronix ST8024
V1.0 5/26
2003-07-02
V
DD
I/O
To Internal
Circuit
Vss (0V)
Vss (0V)
Control Signal
Vss (0V)
V
DD
Output Signal
Control Signal
Application Pins
EIO
1
, EIO
2
Fig. 4 Input/Output Circuit
O
Vss (0V)
V
0
Control Signal 1
Control Signal 3
Control Signal 2
Control Signal 4
V
0
V
12
V
43
V
5
V
SS
(0V)
Application Pins
Y
1
~Y
160
Fig. 5 LCD Drive Output Circuit
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