1/13
December 2001
s
HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 1
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2T74 is an advanced high-speed CMOS
SINGLE D-TYPE FLIP FLOP WITH PRESET
AND CLEAR fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
tecnology.
A signal on the D INPUT is transfered to the Q and
Q OUTPUTS during the positive going transition
of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V2T74
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
74V2T70STR
SOT323-8L
74V2T70CTR
SOT23-8L
SOT323-8L
PRELIMINARY DATA
74V2T74
2/13
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X= Don't care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
6
CLR
Asyncronous Reset -
Direct Input
2
D
Data Input
1
CK
Clock Input
(LOW to HIGH, Edge
Triggered)
7
PR
Asyncronous Set - Direct
Input
5
Q
True Flip-Flop Output
3
Q
Complement Flip-Flop
Output
4
GND
Ground (0V)
8
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
74V2T74
3/13
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occour. Functional operation under these condition is
not implied
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperqture
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 1) (V
CC
= 5.0
0.5V)
0 to 20
ns/V
74V2T74
4/13
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5 to
5.5
2
2
2
V
V
IL
Low Level Input
Voltage
4.5 to
5.5
0.8
0.8
0.8
V
V
OH
High Level Ouput
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
0.55
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1.0
1.0
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
1
10
20
A
I
CC
Additional Worst
Case Supply
Current
5.5
One Input at 3.4V,
other input at V
CC
or GND
1.35
1.5
1.5
mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5
5.0
5.0
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
5.0
(*)
15
4.6
7.3
1.0
8.5
1.0
8.5
ns
5.0
(*)
50
6.1
9.3
1.0
10.5
1.0
10.5
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
5.0
(*)
15
4.8
7.7
1.0
9.0
1.0
9.0
ns
5.0
(*)
50
6.3
9.7
1.0
11.0
1.0
11.0
t
W
CK Pulse Width
HIGH or LOW
5.0
(*)
5.0
5.0
5.0
ns
t
W
PR or CLR Pulse
Width LOW
5.0
(*)
5.0
5.0
5.0
ns
t
s
Setup Time D to CK
HIGH or LOW
5.0
(*)
5.0
5.0
5.0
ns
t
h
Hold Time D to CK
HIGH or LOW
5.0
(*)
0.5
0.5
0.5
ns
t
REM
Removal Time
PR or CLR to CK
5.0
(*)
3.0
3.0
3.0
ns
f
MAX
Maximum Clock
Frequency
5.0
(*)
15
100
160
80
80
MHz
5.0
(*)
50
80
140
65
65
74V2T74
5/13
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
TEST CIRCUIT
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
4
10
10
10
pF
C
PD
Power Dissipation
Capacitance
(note 1)
5.0
f
IN
= 10MHz
22
pF
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