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DATA BRIEFING
This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact
your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29
ST19GF34
Smartcard MCU
With 34 KBytes EEPROM
ST19GF34 FEATURES:
s
ENHANCED 8 BIT CPU WITH EXTENDED
ADDRESSING MODES
s
USER ROM WITH PARTITIONING
s
56
K BYTES OF
SYSTEM ROM
s
1984BYTES OF USER RAM WITH
PARTITIONING
s
34 K BYTES OF USER EEPROM WITH
PARTITIONING
Highly reliable CMOS EEPROM submicron
technology
10 years data retention
100,000 Erase/Write cycles endurance
Separate Write and Erase cycles for fast "1"
programming
1 to 64 bytes Erase or Program
Full support of GSM Toolkit and Javacard im-
plementation
s
SECURITY FIREWALLS FOR MEMORIES
s
VERY HIGH SECURITY FEATURES
INCLUDING EEPROM FLASH PROGRAM
s
8 BIT TIMER WITH INTERRUPT CAPABILITY
s
2 SERIAL ACCESS, ISO 7816-3 COMPATIBLE
s
3V
10% or 5V
10% SUPPLY VOLTAGE
s
POWER SAVING STANDBY MODE
s
CONTACT ASSIGNMENT COMPATIBLE ISO
7816-2
s
ESD PROTECTION GREATER THAN 5000V
4
4
4
4
Micromodule (D4)
Wafer
October 1999
ST19GF34
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HARDWARE DESCRIPTION
The ST19GF34, a member of the ST19 device
family, is a serial access microcontroller especially
designed for very large volume and cost competi-
tive secure portable objects.
The ST19GF34 is based on a STMicroelectronics
8 bit CPU core including on-chip memories: 1984
Bytes of RAM, 56 K Bytes of USER ROM and 34
K Bytes of EEPROM.
RAM, ROM and EEPROM memories can be con-
figured into partitions. Access rules from any
memory partition to another partition are setup by
the user defined Memory Access Control Logic.
It is manufactured using the highly reliable ST
technology.
As all other ST19 family members, it is fully com-
patible with the ISO standards for Smartcard appli-
cations.
SOFTWARE DESCRIPTION
Software development and firmware (ROM code/
options) generation are completed by the ST16-19
HDSE development system.
Figure 1. Block Diagram
SCP 101b/DS
INTERNAL BUS
RESET
SERIAL
I/O
INTER-
FACE
8 BIT
CPU
8 BIT
TIMER
CLOCK
GENERA-
TOR
MODULE
UNPRE-
DICTABLE
NUMBER
GENERATOR
RAM
EEPROM
USER
ROM
SYSTEM ROM
FIREWALL
MEMORY ACCESS FIREWALL
CLK
I/O
GND
Vcc
SYSTEM ROM
SECURITY
ADMINISTRATOR
1984
Bytes
34 K
Bytes
56 K
Bytes
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