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ST20C2/C4 Core
Instruction Set
Reference Manual
72-TRN-273-01
January 1996
2/212
3/212
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
Instruction name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2
Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.5
Error signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.6
Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.7
Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.1
The processor state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.2
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.3
Undefined values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.7.4
Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.7.5
Representing memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.7.6
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.8
Block move registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.9
Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.10 Operators used in the definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.11 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.12 Conditions to instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2
Addressing and data representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1
Word address and byte selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2
Ordering of information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3
Signed integers and sign extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1
Machine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1.1
Process state registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1.2
Other machine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2
The process descriptor and its associated register fields . . . . . . . . . . . . . 24
4
Instruction representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1
Instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.1
An instruction component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.2
The instruction data value and prefixing . . . . . . . . . . . . . . . . . . .25
4.1.3
Primary Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1.4
Secondary instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1.5
Summary of encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.2
Generating prefix sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.1
Prefixing a constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.2
Evaluating minimal symbol offsets . . . . . . . . . . . . . . . . . . . . . . . .29
5
Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contents
4/212
5/212
1
Introduction
This manual provides a summary and reference to the ST20 instruction set for C2 and
C4 cores. The instructions are listed in alphabetical order, one to a page. Descriptions
are presented in a standard format with the instruction mnemonic and full name of the
instruction at the top of the page, followed by these categories of information:
Code: the instruction code;
Description: a brief summary of the purpose and behavior of the instruction;
Definition: a more complete description of the instruction, using the notation
described below in section 1.7;
Error signals: a list of errors and other signals which can occur;
Comments: a list of other important features of the instruction;
See also: for some instructions, a cross reference is provided to other instruc-
tions with a related function.
These categories are explained in more detail below, using the
add instruction as an
example.
1.1
Instruction name
The header at the top of each page shows the instruction mnemonic and, on the right,
the full name of the instruction. For primary instructions the mnemonic is followed by
`n' to indicate the operand to the instruction; the same notation is used in the
description to show how the operand is used.
1.2
Code
For secondar y instructions the instruction `operation code' is shown as the memory
code -- the actual bytes, including any prefixes, which are stored in memory. The
value is given as a sequence of bytes in hexadecimal, decoded left to right. The codes
are stored in memory in `little-endian' format -- with the first byte at the lowest
address.
For primary instructions the code stored in memory is determined partly by the value
of the operand to the instruction. In this case the op-code is shown as `Function
x'
where
x is the function code in the last byte of the instruction. For example, adc (add
constant) is shown as `Function 8'.
Example
The entry for the
add instruction is:
Code: F5