1/11
May 2005
STP9NK80Z
STF9NK80Z
N-CHANNEL 800V -0.9
- 7.5A TO-220/TO-220FP
Zener-Protected SuperMESHTMMOSFET
Table 1: General Features
s
TYPICAL R
DS
(on) = 0.9
s
EXTREMELY HIGH dv/dt CAPABILITY
s
IMPROVED ESD CAPABILITY
s
100% AVALANCHE RATED
s
GATE CHARGE MINIMIZED
s
VERY LOW INTRINSIC CAPACITANCES
s
VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESHTM series is obtained through an
extreme optimization of ST's well established
strip-based PowerMESHTM layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmeshTM products.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
IDEAL FOR OFF-LINE POWER SUPPLIES
s
SMPS
Table 2: Order Codes
Figure 1: Package
Figure 2: Internal Schematic Diagram
TYPE
V
DSS
R
DS(on)
I
D
Pw
STP9NK80Z
STF9NK80Z
800 V
800 V
<1.2
<1.2
7.5 A
7.5 A
150 W
35 W
TO-220
TO-220FP
1
2
3
SALES TYPE
MARKING
PACKAGE
PACKAGING
STP9NK80Z
P9NK80Z
TO-220
TUBE
STF9NK80Z
F9NK80Z
TO-220FP
TUBE
Rev. 1
STP9NK80Z - STF9NK80Z
2/11
Table 3: Absolute Maximum ratings
( ) Pulse width limited by safe operating area
(1) I
SD
7.5A, di/dt
200A/s, V
DD
=
80% V
(BR)DSS
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
Table 5: Avalanche Characteristics
Table 6: Gate-Source Zener Diode
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol
Parameter
Value
Unit
TO-220
TO-220FP
V
DS
Drain-source Voltage (V
GS
= 0)
800
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
800
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C
7.5
7.5 (*)
A
I
D
Drain Current (continuous) at T
C
= 100C
4.7
4.7 (*)
A
I
DM
( )
Drain Current (pulsed)
30
30 (*)
A
P
TOT
Total Dissipation at T
C
= 25C
150
35
W
Derating Factor
1.20
0.28
W/C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5K
)
4000
V
dv/dt (1)
Peak Diode Recovery voltage slope
4.5
V/ns
V
ISO
Insulation Withstand Voltage (DC)
-
2500
V
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
-55 to 150
C
C
TO-220
TO-220FP
Rthj-case
Thermal Resistance Junction-case Max
0.83
3.6
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
C/W
T
l
Maximum Lead Temperature For Soldering
Purpose
350
C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
7.5
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
350
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BV
GSO
Gate-Source
Breakdown Voltage
Igs= 1mA (Open Drain)
30
V
3/11
STP9NK80Z - STF9NK80Z
ELECTRICAL CHARACTERISTICS (T
CASE
=25C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Table 8: DYNAMIC
Table 9: Source Drain Diode
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 1 mA, V
GS
= 0
800
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 C
1
50
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
10
A
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 100A
3
3.75
4.5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 3.75 A
0.9
1.2
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
= 15 V
,
I
D
= 3.75 A
7.5
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
1900
180
38
pF
pF
pF
C
oss eq.
(3)
Equivalent Output
Capacitance
V
GS
= 0V, V
DS
= 0V to 640V
75
pF
t
d(on)
t
r
t
d(off)
t
f
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
V
DD
= 400 V, I
D
= 3.75 A
R
G
= 4.7
V
GS
= 10 V
(see Figure 19)
26
19
58
18
ns
ns
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 640 V, I
D
= 7.5A,
R
G
= 4.7
,
V
GS
= 10V
(see Figure 20)
12
10
24
ns
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 640V, I
D
= 7.5 A,
V
GS
= 10V
(see Figure 22)
60
12
35
84
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
7.5
30
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 7.5 A, V
GS
= 0
1.6
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 7.5 A, di/dt = 100A/s
V
DD
= 35V, T
j
= 25C
(see Figure 20)
530
4.5
17
ns
C
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 7.5 A, di/dt = 100A/s
V
DD
= 35V, T
j
= 150C
(see Figure 20)
690
6.4
17
ns
C
A
STP9NK80Z - STF9NK80Z
4/11
Figure 3: Safe Operating Area for TO-220
Figure 4: Safe Operating Area for TO-220FP
Figure 5: Output Characteristics
Figure 6: Thermal Impedance for TO-220
Figure 7: Thermal Impedance for TO-220FP
Figure 8: Transfer Characteristics
5/11
STP9NK80Z - STF9NK80Z
Figure 9: Transconductance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 11: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 12: Static Drain-source On Resistance
Figure 13: Capacitance Variations
Figure 14: Normalized BVDSS vs Temperature
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