78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PRELIMINARY DATASHEET
- 1 -
JULY 2003
DESCRIPTION
The 78P2343JAT is a low-power, 3-port
DS3/E3/STS1 Line Interface Unit (LIU) with
integrated Jitter Attenuator (JAT). It includes clock
recovery and transmitter pulse shaping functions for
applications using 75-ohm coaxial cable at distances
up to 1350 feet. These applications include
DSLAMs, T1,3/E1,3 digital multiplexers, SONET
Add/Drop multiplexers, PDH equipment, DS3 to
Fiber optic and microwave modems and ATM WAN
access for routers and switches.
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements. It has a
B3ZS/HDB3 ENDEC with a receive line code
violation detector, a loop-back mode, an input
receive MUX that can select a redundant channel, a
clock polarity selection mode, and the ability to
receive a DSX3 monitor signal.
STANDARDS
Jitter Tolerance: Telcordia GR-499-CORE [DS3]
and GR-253-CORE [STS1], ITU-T G.823 [E3]
and G.824 [DS3]
Loss of Signal: ITU-T G.775
Jitter Transfer: ETSI TBR-24 1997 [E3];
Telcordia GR-499-CORE [DS3] and GR-253-
CORE [DS3/STS1]
FEATURES
Transmit and receive interfaces for E3, DS3 and
STS-1 applications
Designed for use with 75 ohm coaxial cable up
to 1350 ft long end-to-end or up to 900 ft long
from a DS3 cross-connect
Receives DS3-high and DSX3 monitor signals
Local and Remote loopback
Selectable B3ZS/HDB3 ENDEC with line code
violation detector
Standards-based LOS function
Optional serial-port based mode selection and
channel status monitoring
Receiver AGC corrects for up to 6dB of flat loss
Adaptive digital clock recovery (uses line-rate
reference clock input)
Receive output clock maintains nominal line-rate
frequency at all times
Fully integrated Jitter Attenuation function
provided for all line rates (no external VCXO
required)
Jitter Attenuator configurable for transmit or
receive path
Transmit line fault monitor
Requires no external current-setting resistor or
loop filter components
Single 3.3V supply operation
Available in 100-pin Exposed Pad JEDEC LQFP
BLOCK DIAGRAM
LINN
LINP
LOUTN
LOUTP
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
DS3
TXEN
LLBKA
LLBKB
RLBK
PDTX
ENDEC
Signals from
Adjacent Port
TXNW
Control
Registers
CS
SCK
SDI
SDO
E3
LBO
Master
Bias
Generator
CKREF
Each Channel
CKREF
LOS
MON
Attenuator
Power
Distribution
B3ZS /
HDB3
Encoder
Data
Detector
B3ZS /
HDB3
Decoder
Adaptive
Equalizer
Signal
Detector
Transmit
Monitor
Pulse
Shaper
Controls
Jitter
Attenuator
Flags
TCLKP
RCLKP
Clock
Recovery
AGC
PDRX
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 2 -
FUNCTIONAL DESCRIPTION
The 78P2343JAT contains all the necessary
transmit and receive circuitry for connection
between E3, DS3, or STS-1 line interfaces and
digital Framer/Mapper ICs.
OPERATING RATE
The Master Control Register (MSCR) determines
which mode the device operates in according to the
table below. The MSL0 pin is also provided for
mode selection in applications without a serial
control interface. Upon power-up or reset, the state
of the MSL0 pin is sensed and mapped into the DS3
and E3 register bits representing the appropriate
mode of operation. After power-up/reset, the state of
the MSL0 pin is ignored.
Standard
MSL0 pin
DS3 bit
E3 bit
E3 L
0
1
DS3 H
1
0
STS-1 Z 0 0
STS-1 Z 1 1
RECEIVER OPERATION
The receiver input is either transformer-coupled or
capacitor-coupled to the line signal. In applications
where the highest performance and isolation are
required, a 1:1 transformer is used in the receive
path. In applications where isolation is provided
elsewhere in the circuit, capacitor coupling can be
used. The receiver input should be line terminated
externally with a termination resistor.
The AMI signal first enters an AGC, which has a
selectable gain range setting. In normal operation,
the AGC can compensate for signals with up to 6dB
of flat loss. When Receiver Monitor Mode is
enabled, the AGC can compensate for a DSX3
monitor signal with 16 to 20 dB of flat loss. The
signal then enters a high performance adaptive
equalizer. The equalizer is designed to overcome
inter-symbol interference caused by long cable
lengths. Because the equalizer is adaptive, the
circuit will work with all square-shaped signals such
as DS3-high or 34.368 Mbit/s E3. The variable gain
differential amplifier automatically controls the gain
to maintain a constant voltage level output
regardless of the input voltage level.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a digital PLL, which uses a line-rate
reference clock frequency applied to the CKREF pin.
The jitter tolerance of 78P2343 meets the
requirements of ITU-T G.823 for E3 rates; the
requirements of ITU-T G.824, GR-499 (Cat I and II)
for DS3 rates; and the requirements of GR-253 for
STS1 rates.
Without the Jitter Attenuator, the jitter transfer
function meets the requirements of GR-499 for
Category II DS3 interfaces.
When the Jitter Attenuator is enabled, the
78P2343JAT meets the requirements of GR-499
and GR-253 for all categories of DS3/STS1
equipment and the ETSI TBR-24 requirements for
E3 rates. To check conformance with other
standards, please refer to the JITTER
ATTENUATOR TRANSFER FUNCTION section for
more detailed info.
RECEIVER MONITOR MODE
When in monitor mode, 20dB of flat gain is applied
to the incoming signal before it is fed to the receive
equalizer. This mode is controlled by the MON bit in
the Mode Control Register.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 3 -
LOCAL LOOPBACK AND REDUNDANCY MUX
Receivers 1 and 2 have a 4-input MUX as shown in
the adjacent figure. In multiport applications where
redundant channels are required, the receiver MUX
can be configured to provide the necessary
multiplexing functions. This allows the user to use
one port as a redundant monitor for the other port.
The tables below show the register settings for
selecting the desired receiver input source.
LLBKA
(Port 1)
LLBKB
(Port 1)
Receiver #1 Input
Source
0 0
LINP1/LINN1
0 1
LOUTP1/LOUTN1
1 0
LINP2/LINN2
1 1
LOUTP2/LOUTN2
LLBKA
(Port 2)
LLBKB
(Port 2)
Receiver #2 Input
Source
0 0
LINP2/LINN2
0 1
LOUTP2/LOUTN2
1 0
LINP1/LINN1
1 1
LOUTP1/LOUTN1
LLBKB
(Port 3)
Receiver #3 Input
Source
0 LINP3/LINN3
1 LOUTP3/LOUTN3
Note: The LLBKA and LLBKB bits are located in the
Mode Control Register (MDCR). The Register
Control bit, REGEN, should be enabled when using
the register settings to avoid conflict with external
loopback setting pins.
Transmitter
#1
Receiver
#1
00
01
10
11
Transmitter
#2
Receiver
#2
00
01
10
11
Transmitter
#3
Receiver
#3
0
1
LOUTP1, LOUTN1
LINP1, LINN1
LOUTP2, LOUTN2
LINP2, LINN2
LOUTP3, LOUTN3
LINP3, LINN3
LLBKA,B(1)
LLBKA,B(2)
LLBKB(3)
When serial interface control is not available, the
respective LPBKx pin for each of the channels can
also be used to activate local loopback mode as
shown below. Note that redundant channel modes
can only be activated using the serial interface.
LPBKx
pin
Loopback Mode
L
Normal Operation
Same as LLBKA,B = `00'
Z
Remote (Digital) Loopback
Same as RLBK = `1'
H
Local (Analog) Loopback
Same as LLBKA,B = `01'
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 4 -
SIGNAL DETECT
When the received signal is below a minimum
threshold, the corresponding LOS signal (bit) is
asserted. A time delay is provided before this output
is active so that transient interruptions do not cause
false indications. The LOS signal can also be used
to trigger an interrupt on the INTRx pin when serial
interface control is not available. This is controlled
by setting the RXER bit in the Interrupt Control
Register (INTC).
Note: In DS3 or STS-1 mode, when LBO is not
enabled, the transmitters have to be properly
terminated to ensure reliable LOS detection. If a
transmitter is not terminated, the resultant 2x signal
is large enough to couple to the neighboring
receivers through the ESD diodes, causing false
Signal Detect indication.
B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION
DETECT
The 78P2343JAT includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). The ENDEC function
can be enabled or disabled through pin selection or
register setting. When the
ENDEC is enabled, the
decoder generates a composite NRZ logic data
stream following the B3ZS (for DS3/STS-1) or HDB3
(for E3) substitution codes via the RPOS pin as
shown below:
ENDEC
ENDEC
ENDEC
ENDEC
bit/pin
RPOSx RNEGx
0 / L
NRZ data
Receive Line Code
Violation Indicator
1 / H
Positive AMI
Negative AMI
The decoder also detects Receive Line Code
Violations (RLCV) and outputs a pulse via the
RNEG pin. Three different classes of line code
violations are detected.
1) Too many zeros: More than two (three)
consecutive zeros in B3ZS (HDB3) mode.
2) Not enough zeros between bipolar pulse (B)
and bipolar violation pulse (V): (B,V) for B3ZS.
(B,V) or (B,0,V) for HDB3.
3) Code violation: Even number of bipolar pulses
(B) detected between bipolar violation pulses
(V).
On the transmit side, when the ENDEC is enabled,
NRZ input data is encoded to Positive and Negative
AMI logic data following the B3ZS (for DS3/STS-1)
or HDB3 (for E3) substitution codes. The NRZ data
is input to the TPOS pin as shown below:
ENDEC
ENDEC
ENDEC
ENDEC
bit/pin
TPOSx TNEGx
0 / L
NRZ data
`Don't Care'
1 / H
Positive AMI
Negative AMI
TRANSMITTER OPERATION
Transmitters 1-3 are enabled by their corresponding
TXEN bit. When enabled, each transmitter accepts
logic level clock (TCLKx), positive data (TPOSx) and
negative data (TNEGx) signals and generates
current pulses on the LOUTPx and LOUTNx pins.
When properly connected to a 1:2CT center-tapped
transformer, an AMI pulse is generated which can
drive a 75
coaxial cable.
When the recommended transformer is used and
when DS3 mode is selected, the transmitted pulse
shape at the end of the 75
terminated cable of 0 to
450 feet will fit the DS3 template in ANSI T1.102-
1993 and Telcordia GR-499-CORE standard
documents. For STS-1 applications, the transmitted
pulse for a short cable meets the requirements of
Telcordia GR-253-CORE.
For E3 applications, the transmitted pulse for a short
cable meets the requirements of ITU-T G.703.
In either DS3 and STS-1 modes, the LBOx pin or
LBO bit should be set high for short cable (< 225 ft),
and should be set low for long cable (> 225 ft). The
LBO settings are ignored in E3 mode.
RCLK/TCLK POLARITY REVERSAL
To simplify the interface with various framer circuitry,
TCLK polarity can be internally inverted by setting
the TCLKP bit, and RCLK polarity can be inverted
by setting the RCLKP bit. Both bits are located in
the Master Control Register (MSCR).
REMOTE (DIGITAL) LOOPBACK
When the Register Control bit, REGEN, is disabled
and the LPBKx
pin is floating; or when the Register
Control bit, REGEN, is enabled and the RLBK bit is
set, RCLKx, RNEGx, and RPOSx outputs are
internally looped back to the TCLKx, TNEGx, and
TPOSx inputs respectively.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 5 -
LINE BUILD-OUT
The Line Build-Out (LBO) function controls the
transmit amplitude and pulse shape in DS3 and
STS-1 modes. The selection of LBO depends on
the amount of cable the transmitter is connected to.
When less than 225 ft of cable is used, the
corresponding LBOx pin or LBO bit should be high.
When 225ft or more cable is used the corresponding
LBO setting (LBOx pin or LBO bit) should be low.
LBO can be controlled either from pins or from
register settings, depending on the status of the
Register Control bit, REGEN.
TRANSMIT ENABLE
The TXEN bit in the Mode Control Register controls
the transmitter output. When logic zero, the
transmitter output is disabled. This feature is used to
disable ports as well as to multiplex two or more
transceivers to one port. The transmitter of any port
can also be disabled by floating the respective LBOx
pin, in which case it will also power-down the entire
transmitter. See section on the Power-Down
Function for more info.
TRANSMIT MONITOR
The transmit monitor function detects activity on the
transmitter output at the LOUTPx and LOUTNx pins.
When there is a transmitter fault, in the case of an
open or short on the chip, the transformer, or the
circuit board, the transmit signal amplitude will be
altered. The transmit monitor detects the amplitude
of the driven signal. The TXNW signal (bit) goes
high when the amplitude of the transmit signal is
outside a valid amplitude range. When the signal
amplitude is either too high or too low for longer than
a specified duration, the TXNW bit goes high. The
TXNW signal can be also used to trigger an interrupt
on the INTRx pin when serial interface control is not
available. This is accomplished by setting the TXER
bit in the Interrupt Control Register (INTC).
JITTER ATTENUATOR
Jitter Attenuation function is provided on-chip. The
Jitter Attenuator can be configured to be in the
transmit or the receive path. When configured in the
transmit path, the input clock at TCLK pin is passed
through a very low bandwidth digital PLL. The
corresponding transmit data is buffered into a FIFO
and clocked out using the de-jittered output clock of
the PLL. When configured in the receive path, the
recovered clock is passed through the low
bandwidth digital PLL, and the corresponding
receive data is buffered into the FIFO and clocked
out using the de-jittered clock.
The Jitter Attenuator can be configured
independently for each channel by writing to the
Jitter Attenuator Control Register (JACR) as follows:
JAEN
bit
JASL
bit
Jitter Attenuator Mode
0
X
Jitter Attenuator disabled
1
0
Jitter Attenuator configured
to be in the receive path
1
1
Jitter Attenuator configured
to be in the transmit path
When serial interface control is not available, the
MSL1 pin is provided for Jitter Attenuator mode
selection. Upon power-up or reset, the state of the
MSL1 pin is sensed and mapped into the JAEN and
JASL register bits for all channels, representing the
appropriate mode of operation. After power-up or
reset, the state of the MSL1 pin is ignored. The
state of the MSL1 pin, and the corresponding Jitter
Attenuator configuration is shown below.
MSL1 pin
Jitter Attenuator Mode
L
Jitter Attenuator in receive path
H
Jitter Attenuator in transmit path
Z
Jitter Attenuator disabled
PLL Bandwidth
A PLL response with effectively one pole below 27
Hz is adequate to meet the ETSI TBR24 E3
standards. A PLL response with one pole below 40
Hz is adequate to meet the GR-499 (Cat I) DS3
standards. Either of the two bandwidths can be
selected via register setting. In either high or low
bandwidth mode, the PLL bandwidth is proportional
to the data rate as follows:
Line Rate
JABW bit
PLL Bandwidth (Hz)
0 13
E3
1 188
0 17
DS3
1 245
0 20
STS1
1 283
The default state of the JABW bit depends on which
line-rate is selected through the MSL0 pin. If E3 or
DS3 mode is selected, the default state is `0'. If
STS1 mode is selected, the default state is `1'.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 6 -
Elastic Store Depth
To optimize the trade-off between data latency and
clock wander tolerance, the FIFO elastic store depth
can be selected through the serial port by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
ESP[1:0]
bits
Elastic Store Depth
00 Pass-Through
mode
01 16
UI
10 32
UI
11
64 UI (default)
The Elastic Store Depth selects the nominal FIFO
read pointer address. The total or maximum elastic
store depth is set to be twice as deep as the nominal
pointer address. The circular buffer length is always
twice as long as the nominal pointer address.
POWER-DOWN FUNCTION
Power-down control is provided to allow the
transceivers to be shut off individually. Transmit and
receive power-down can be set independently via
the PDTX and PDRX bits in the Mode Control
Register. Floating the respective LBOx pin can also
set PDTX for each channel. The Serial Control
Interface and Configuration Registers are not
affected by power-down.
INTERNAL POWER-ON RESET
The 78P2343JAT includes on-chip Power-On Reset
(POR) function to ensure the serial-port registers are
initialized to known default states upon power-up.
This reset signal also sets all state machines within
the transceivers to nominal operational states. The
internal reset signal is also brought out to the
POR
pin. This pin is a multi-function pin which allows for
the following:
1) Override the internal POR signal by driving in an
external active-low reset signal;
2) Monitor the state of the internal POR signal (for
test and debug only);
3) Add external capacitor to delay the release of
the internal power-on reset signal to allow the
MSL0 pin to stabilize prior to release of reset
(approximately 8
s per nF added).
The internal resistance of the POR pin is
approximately 5k
.
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2343JAT. It is
used for mode settings, diagnostics and test, and
the retrieval of status and performance information.
The serial interface consists of four pins: Chip Select
(CS), Serial Clock (SCK), Serial Data In (SDI), and
Serial Data Out (SDO). The CS pin initiates the
read and write operations. It can also be used to
select a particular device allowing SCK, SDI and
SDO to be bussed together. SCK is the clock input
that times the data on SDI and SDO. Data on SDI is
latched in on the rising-edge of SCK, and data on
SDO is clocked out using the falling edge of SCK.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only
during the duration when register data is being
clocked out. Read data is clocked out least
significant bit (LSB) first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 7 -
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port
Address Sub-Address
Read/
Write
Assignment PA[3] PA[2] PA[1] PA[0] SA[2] SA[1] SA[0] R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Sub
Addr
Reg.
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
MSCR
(R/W)
Master Control
REGEN
<0>
DS3
<X>
E3
<X>
ENDEC
<0>
RCLKP
<0>
TCLKP
<0>
--
SRST
<0>
1
INTC
(R/W)
Interrupt Control
INPOL
<0>
-- -- --
JAFLG
<0>
JAER
<0>
RXER
<1>
TXER
<1>
2
RSVD
Reserved
--
--
--
--
--
--
--
--
3
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
4
RSVD
Reserved
--
--
--
--
--
--
--
--
5
RSVD
Reserved
--
--
--
--
--
--
--
--
6
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
7
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
b) PA[3:0] = 1-3 : Port-Specific Registers
Sub
Addr
Reg.
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
MDCR
(R/W)
Mode Control
PDTX
<0>
PDRX
<0>
LBO
<1>
LLBKA
<0>
LLBKB
<0>
RLBK
<0>
MON
<0>
TXEN
<1>
1
STAT
(R/O)
Status Monitor
FERR
-- -- --
LOS TXNW -- SGLO
2
RSVD
Reserved
<1>
<1>
<0>
<1>
<0>
<1>
<0>
<0>
3
JACR
(R/W)
Jitter Attenuator
Control
JAEN
<X>
JASL
<X>
JLBK
<0>
<0>
ESP[1]
<1>
ESP[0]
<1>
<0>
JABW
<X>
4
RSVD
Reserved
--
--
--
--
--
--
--
--
5
RSVD
Reserved
<0>
--
--
<0>
<0>
<0>
<0>
<0>
6
RSVD
Reserved
--
--
--
--
--
--
--
--
7
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
Note: Shaded registers in Register Table are reserved for TDK internal use only. Accessing reserved or
undefined registers may cause undesirable operation.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 8 -
REGISTER DESCRIPTION
(continued)
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
R/O
Read only
R/W
Read or Write
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT NAME TYPE DFLT
VALUE
DESCRIPTION
7 REGEN R/W 0
Register Control Enable:
0 : Pin selection overrides register settings
1 : Device is controlled via register set.
NOTE: Pin 15 (
ENDEC
ENDEC
ENDEC
ENDEC) must be tied low when REGEN is enabled.
6 DS3
R/W X
5 E3 R/W X
Line Speed Selection: Selects the line speed of all channels as well as
the input clock frequency at the CKREF pin.
[DS3 E3] = 00 : STS-1 (51.840MHz)
01 : E3 (34.368MHz)
10 : DS3 (44.736MHz)
11 : STS-1 (51.840MHz)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset.
4
ENDEC
R/W 0
Encoder/Decoder Disable:
0 : selects NRZ digital data interface
1 : selects AMI digital data interface
NOTE: Relevant only when the REGEN bit is set. Otherwise,
ENDEC pin
selection prevails.
3 RCLKP R/W 0
RCLK Polarity Selection:
0 : Receive Data clocked out on the falling-edge of RCLK
1 : Receive Data clocked out on the rising-edge of RCLK
2 TCLKP R/W 0
TCLK Polarity Selection:
0 : Transmit Data clocked in on the rising-edge of TCLK
1 : Transmit Data clocked in on the falling-edge of TCLK
1 RSVD R/O X Reserved
0 SRST R/W 0
Register Soft-Reset: When this bit is set, all registers are reset to their
default values. Also resets Jitter Attenuator to "centered" states. This
register bit is self-clearing.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 9 -
REGISTER DESCRIPTION
(continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the respective interrupt pin (INTRx) for each of the ports to be
activated. User may set as many bits as required.
BIT NAME TYPE DFLT
VALUE
DESCRIPTION
7 INPOL R/W 0
Interrupt Pin Polarity Selection:
0 : Interrupt output is active-low
1 : Interrupt output is active-high
6:3 RSVD R/O
0 Reserved
2 JAER R/W 0
Jitter Attenuator Error Event:
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
1 RXER R/W 1
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
0 TXER R/W 1
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 10 -
REGISTER DESCRIPTION
(continued)
PORT-SPECIFIC REGISTERS
For PA[3:0] = N = 1-3 only. Accessing a register with port address greater than 3 constitutes an invalid
command, and the read/write operation will be ignored.
ADDRESS N-0: MODE CONTROL REGISTER
BIT NAME TYPE DFLT
VALUE
DESCRIPTION
7 PDTX R/W 0
Transmitter Power-Down:
0 : Normal Operation
1 : Power-Down
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin
selection prevails.
6 PDRX R/W 0
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
5 LBO R/W 1
Transmitter Line Build-Out (DS3 and STS-1 only):
0 :
225ft of cable attached to the cross-connect
1 : < 225ft of cable attached to the cross-connect
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin
selection prevails.
4 LLBKA R/W 0
3 LLBKB R/W 0
Local (Analog) Loopback Mode Selection:
[LLBKA LLBKB] = 00 : Normal operation
01 : Transmitter loopback
10 : Adjacent receiver input
11 : Adjacent transmitter loopback
NOTE: Relevant only when the REGEN bit is set. Otherwise, LPBKx pin
selection prevails.
2 RLBK R/W 0
Remote (Digital) Loopback Enable:
0 : Normal Operation
1 : Loops RCLK, RPOS, and RNEG back onto TCLK, TPOS, and TNEG
NOTE: Relevant only when the REGEN bit is set. Otherwise, LPBKx pin
selection prevails.
1 MON R/W 0
Monitor Mode Enable: Used for reception of split-off signals that are flat
attenuated by at least 16dB but no more than 20dB.
0 : Disable
1 : Enable
0 TXEN R/W 1
Transmitter Output Enable:
0 : Transmit driver is disabled
1 : Normal Operation
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin
selection prevails.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 11 -
REGISTER DESCRIPTION
(continued)
ADDRESS N-1: STATUS MONITOR REGISTER
BIT NAME TYPE DFLT
VALUE
DESCRIPTION
7 FERR R/O X
Jitter Attenuator FIFO Error Flag:
This bit is set whenever a FIFO overflow or underflow occurred. It is
reset after a read operation to this register.
0 : Proper Operation
1 : FIFO Overflow/Underflow
6:4 RSVD R/O X Reserved
3 LOS R/O X
Loss-of-Signal Indication:
0 : Signal Detector detecting a valid receive input signal
1 : Standards-based Loss-of-Signal indication
NOTE: RPOSx and RNEGx are forced low when LOS='1'. RCLK will
continue to output a line rate clock
2 TXNW R/O X
Transmitter Not-Working Indication:
0 : Transmitter OK
1 : Transmitter not working
1 RSVD R/O X Reserved
0 SGLO R/O X
Signal Low Indication:
0 : Receive signal level OK
1 : Receive signal level too low / Loss of signal
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 12 -
REGISTER DESCRIPTION
(continued)
ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER
BIT NAME TYPE DFLT
VALUE
DESCRIPTION
7 JAEN R/W X
Jitter Attenuator Enable:
0 : Disables jitter attenuation function
1 : Enables jitter attenuation function
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
6 JASL R/W X
Jitter Attenuation Selection:
0 : Jitter Attenuator on the receive path
1 : Jitter Attenuator on the transmit path
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
5 JLBK R/W 0
Jitter Attenuator Local Loopback Enable:
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and
RCLKx, RPOSx, RNEGx connected to JAT output
NOTE: If both RLBK and JLBK bits are set, RLBK mode takes priority.
4
RSVD
R/W
0
Reserved. Must be set to zero.
3:2
ESP
[1:0]
R/W 11
FIFO Elastic Store Pointer Selection:
00 : Pass-through
01 : 8 UI
10 : 16 UI
11 : 32 UI
1
RSVD
R/W
0
Reserved. Must be set to zero.
0
JABW
R/W X
Jitter Attenuator Bandwidth Selection:
0 : Low bandwidth
1 : High bandwidth
(see JAT Bandwidth Selection Table on page 5)
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset. If the state of the MSL0 pin
selects E3 or DS3 mode, the default value of JABW is `0'. If the state of
the MSL0 pin selects STS1 mode, the default value of JABW is `1'.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 13 -
PIN DESCRIPTION
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
A
Analog Pin
CIT
CMOS 3-State Input
CI
CMOS Digital Input
CO
CMOS Digital Output
CIU
CMOS Digital Input w/ Pull-up
COZ
CMOS Tristate Digital Output
CID
CMOS Digital Input w/ Pull-down
S
Supply
CIS
CMOS Schmitt Trigger Input
G
Ground
TRANSMITTER PINS
NAME PIN
TYPE
DESCRIPTION
TPOSx
23, 31
39
CI
Transmit Positive Data/Transmit NRZ: When
ENDEC bit ='1', a logic
one on this pin generates a positive AMI pulse on the coax. This pin
should not be high at the same time that corresponding TNEGx is high.
When
ENDEC bit ='0', data on this pin is encoded and converted into
positive and negative AMI pulses.
TNEGx
24, 32
40
CI
Transmit Negative Data: When
ENDEC bit ='1', a logic one on this pin
generates a negative AMI pulse on the coax. This pin should not be
high at the same time that corresponding TPOSx is high. When
ENDEC bit ='0', this pin is ignored.
TCLKx
25, 33
41
CIS
Transmitter Clock Input: This signal is used to latch the respective
TPOSx and TNEGx signals into the 78P2343JAT.
LOUTPx
LOUTNx
98, 92
85
99, 93
86
A
Line Out: Differential AMI Outputs. Requires a 1:2CT center-tapped
transformer and a shunt termination resistor. See APPLICATION
INFORMATION section for more info.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 14 -
PIN DESCRIPTION
(continued)
RECEIVER PINS
NAME PIN
TYPE
DESCRIPTION
CKREF
57 CIS
Reference Clock Input: This clock should be from a clean source
(
20 ppm) and represents the line-rate frequency as follows:
E3 : 34.368 MHz
DS3: 44.736 MHz
STS-1: 51.840 MHz
RCLKx
27, 35
43
CO
Receive Clock: Recovered receive clock.
Note: During LOS conditions, RCLKx will continue to output a line
rate clock
RNEGx
28, 36
44
CO
Receive Negative Data: When
ENDEC bit ='1', this pin indicates
reception of a negative AMI pulse on the coax. When
ENDEC bit ='0',
this pin outputs a one when a receive line code violation is detected.
RPOSx
29, 37
45
CO
Receive Positive Data/NRZ Data: When
ENDEC bit ='1', this pin
indicates reception of a positive AMI pulse on the coax cable. When
ENDEC bit ='0', it outputs decoded NRZ data.
LINPx
LINNx
96, 90
83
95, 89
82
A
Line In: Differential AMI Inputs. Should be 1:1 transformer-coupled
and terminated with a shunt resistor. See APPLICATION
INFORMATION section for more info.
CONTROL AND STATUS PINS
NAME PIN
TYPE
DESCRIPTION
MSL0
19 CIT
Data-Rate Mode Selection:
Low = E3 mode
High = DS3 mode
Float = STS-1 mode
NOTE: Pin state is latched-in on rising-edge of
POR signal
MSL1
20 CIT
Jitter Attenuator Mode Selection:
Low = JAT in Receive path
High = JAT in Transmit path
Float = JAT is bypassed
NOTE: Pin state is latched-in on rising-edge of
POR signal
POR
14 A
Chip Reset (active-low):
Forces hardware reset on device. See description on
Internal Power-
on Reset
for complete use of this pin.
ENDEC
15 CID
ENDEC Enable (active-low):
Set high to disable internal ENDEC function.
NOTE: Relevant only when the REGEN bit is `0'.
Pin must be held
low when the REGEN bit is set.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 15 -
PIN DESCRIPTION
(continued)
CONTROL AND STATUS PINS (continued)
LBOx
5, 6
7
CIT
Line Build-Out:
Low = Used with 225ft or more of cable.
High = Used with less than 225ft of cable.
Float = Disable and power down transmitter. [TXEN=0; PDTX=1]
NOTE: Relevant only when the REGEN bit is `0'. Pin state sampled
approximately once every 0.5ms.
LPBKx
10, 11
12
CIT
Loopback Enable:
Low = Normal Operation
High = Local Loopback. Transmitter looped back to Receiver
Float = Remote Loopback. Receiver looped back to Transmitter
NOTE: Relevant only when the REGEN bit is `0'. Pin state sampled
approximately once every 0.5ms.
INTRx
64, 63
62
CO
Interrupt Flag:
This pin is normally high when the INPOL bit is `0' (default), and
normally low when the INPOL bit is `1'. When an interrupt event
occurs (as defined in the Interrupt Control Register description), the
respective INTRx pin will change state.
SERIAL-PORT PINS
NAME PIN
TYPE
DESCRIPTION
CS 65
CI
Chip Select: High during write and read operations. Low disables the
serial port. While CS is low, SDO remains in high impedance state,
and SDI and SCK activities are ignored.
SCK
66
CIS
Serial Clock: Controls the timing of SDI and SDO.
SDI 68
CI
Serial Data Input: Inputs mode and address information. Also inputs
register data during a Write operation. Both address and data are input
least significant bit first.
SDO 67
COZ
Serial Data Output: Outputs register information during a Read
operation. Data is output least significant bit first.
POWER AND GROUND PINS
It is recommended that all supply pins be connected to a single power supply plane and all ground pins be
connected to a single ground plane.
NAME PIN
TYPE
DESCRIPTION
VCC
1, 2, 3, 4, 17,
59, 72, 73,
74, 75
S Analog
Power
Supply
GND
18, 60, 78,
81, 84, 87,
91, 94, 97,
100
S Analog
Ground
VCCD
16, 22, 30,
38, 46, 54,
55, 58
S Digital
Power
Supply
GNDD
9, 21, 26, 34,
42, 50, 56, 69
S Digital
Ground
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 16 -
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these limits may permanently damage the device.
PARAMETER RATING
Supply Voltage (VCC/VCCD)
-0.5 to 4.0 VDC
Storage Temperature
-65 to 150 C
Junction Temperature
-40 to 125 C
Pin Voltage (LOUTPx, LOUTNx)
VCC + 1.5 VDC
Pin Voltage (all other pins)
-0.3 to (VCC+0.6) VDC
Pin Current
100 mA
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges.
PARAMETER RATING
DC Voltage Supply (VCC/VCCD)
3.0 to 3.6 V
Ambient Operating Temperature
-40 to 85C
DC CHARACTERISTICS:
PARAMETER SYMBOL CONDITIONS
MIN
NOM
MAX
UNIT
Supply Current
Idd
All channels on
DS3 mode
JAT Enabled:
JAT Disabled:
257
240
282
263
mA
mA
Receive-only Supply Current
Iddr
All channels PDTX = 1
DS3 mode
JAT Enabled:
JAT Disabled:
91
73
mA
mA
Transmit-only Supply Current
Iddt
All channels PDRX = 1
DS3 mode
JAT Enabled:
JAT Disabled:
173
155
mA
mA
Supply Current per Port
(including transmitter current
through transformer)
Iddx
DS3 mode
JAT Enabled:
JAT Disabled:
82
76
mA
mA
Power-Down Current
Iddq
DS3 mode
PDTX = 1, PDRX = 1
All clocks off
11
15
mA
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 17 -
ELECTRICAL SPECIFICATIONS
(continued)
ANALOG PINS CHARACTERISTICS:
The following table is provided for informative purpose only. Not tested in production.
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
LINPx and LINNx
Common-Mode Bias Voltage
Vblin
Ground reference
1.9 2.25 2.6 V
LINPx and LINNx Differential
Input Impedance
Rilin
10 k
POR Input Impedance
Ripor
5
k
DIGITAL I/O CHARACTERISTICS:
Pins of type CI, CIU, CID:
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Input Voltage Low
Vil
0.8
V
Input Voltage High
Vih
2.0
V
Input Current
Iil, Iih
-1
1
A
Pull-up Resistance
Rpu
Type CIU only
38
56
78
k
Pull-down Resistance
Rpd
Type CID only
38
56
78
k
Input Capacitance
Cin
8
pF
Pins of type CIS:
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Low-to-High Threshold
Vt+
1.3
1.7
V
High-to-Low Threshold
Vt-
0.8
1.2
V
Input Current
Iil, Iih
-1
1
A
Input Capacitance
Cin
8
pF
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 18 -
ELECTRICAL SPECIFICATIONS
(continued)
Pins of type CIT:
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Input Voltage Low
Vtil
0.8
V
Input Voltage High
Vtih
2.0
V
Minimum impedance to be
considered as "float" state
Rtiz
30
k
Pins of type CO and COZ:
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Output Voltage Low
Vol
Iol = 8mA
0.4
V
Output Voltage High
Voh
Ioh = -8mA
2.4
V
Output Transition Time
Tt
C
L
= 20pF; (20-80%)
6
ns
Pin Capacitance
Cout
8
pF
Effective Source Impedance
Rsrc
30
Tristate Output Leakage
Current
Iz Type
COZ
only
-1
1
A
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 19 -
ELECTRICAL SPECIFICATIONS
(continued)
SERIAL-PORT TIMING CHARACTERISTICS:
PARAMETER SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
CS or SDI to SCK setup time
t
su
4
ns
CS or SDI to SCK hold time
t
h
4
ns
SCK to SDO propagation
delay
t
prop
5
12 ns
1
SA0
SA1
SA2
PA0
PA1
PA2
PA3
Z
SEN
SCK
SDI
SDO
t
su
t
h
X
X or Z
t
su
t
h
D0
D1
D2
D3
D4
D5
D6
D7
Z
t
prop
Read Operation
0
SA0
SA1
SA2
PA0
PA1
PA2
PA3
D0
D1
D2
D3
D4
D5
D6
D7
Z
SEN
SCK
SDI
SDO
t
su
t
h
X
X
t
su
t
h
Write Operation
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 20 -
ELECTRICAL SPECIFICATIONS
(continued)
TRANSMITTER TIMING CHARACTERISTICS:
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Clock Duty Cycle
TTCF/TTC
40
60
%
Setup Time
TTDPS
2.5
ns
Hold Time
TTDPH
2.5
ns
TIMING DIAGRAM: Transmitter Waveforms (E3/DS3/STS-1)
TCLK
TCLKP=LOW
TCLK
TCLKP=HIGH
TPOS
TNEG
TTC
TTDPS
TTDPH
TTDNS
TTDNH
TTCF
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 21 -
ELECTRICAL SPECIFICATIONS
(continued)
RECEIVER TIMING CHARACTERISTICS:
PARAMETER SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
CKREF Duty Cycle
--
40
60
%
CKREF Frequency Stability
-- w.r.t.
line-rate
frequency
-20 +20
ppm
RCLK Duty Cycle
TRCF/TRC
40
60
%
Data Propagation Delay
TPROP
-2
3
ns
TIMING DIAGRAM:
Receive Waveforms (E3/DS3/STS-1)
RCLK
RCLKP=LOW
RCLK
RCLKP=HIGH
RPOS
RNEG
RECEIVE LINE
INPUT (REF)
(LINP,LINN)
TRC
TRCF
TPROP
TPROP
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 22 -
ELECTRICAL SPECIFICATIONS
(continued)
DS3 TRANSMITTER
PARAMETER CONDITION MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at LOUTP/LOUTN pins
w/ 37.5
load and LBO pin held
high.
700 800 850 mVpk
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse peaks.
0.9 1.1
Transmitter Power
at 22.368 MHz
All ones pattern, 3kHz bandwidth
-1.8
+5.7
dBm
Harmonic Power
at 44.736 MHz
All ones pattern
Power below fundamental at
22.368MHz
-20
dBm
STS-1 TRANSMITTER
PARAMETER CONDITION
MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at LOUTP/LOUTN pins
w/ 37.5
effective load and LBO
pin held high.
700 825 950 mVpk
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive and
negative pulses measured at pulse
peaks.
0.9 1.1
Transmitter Power
PRBS15 pattern band-limited to
207.36MHz.
-2.7 +4.7
dBm
E3 TRANSMITTER
PARAMETER CONDITION
(see timing diagram)
MIN TYP MAX UNIT
Transmitter Amplitude
Measured at LOUTP/LOUTN pins
w/ 37.5
load.
900 1000 1100 mVpk
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive and
negative pulses measured at pulse
centers
0.95 1.05
Transmitter Pulsewidth Mismatch
Ratio of widths of positive and
negative pulses measured at pulse
half amplitude
0.95 1.05
Transmitter Pulsewidth
Measured at LOUTP/LOUTN pins
14.8
ns
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 23 -
ELECTRICAL SPECIFICATIONS
(continued)
E3 TRANSMIT PULSE TEMPLATE
17 ns
8.65 ns
14.55 ns
12.1 ns
24.5 ns
29.1 ns
0.1
0.1
0.1
0.1
0.1
0.1
0.2
0.2
0
0.5
1.0
0.2
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 24 -
ELECTRICAL SPECIFICATIONS
(continued)
DS3 TRANSMIT PULSE TEMPLATE
Time axis range (UI)
Normalized amplitude equation
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.36 < T < 1.4
0.08+0.407 e
-1.84(T-0.36)
LOWER CURVE
-0.85 < T < -0.36
-0.03
-0.36 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
Nor
m
aliz
ed Am
plitude
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 25 -
ELECTRICAL SPECIFICATIONS
(continued)
STS-1 TRANSMIT PULSE TEMPLATE
STS-1 (Transmit template specs)
Time axis range (T)
Normalized amplitude equation (A)
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.26 < T < 1.4
0.1+0.61 e
-2.4(T-0.26)
LOWER CURVE
-0.85 < T < -0.38
-0.03
-0.38 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
N
o
r
m
aliz
ed A
m
plitude
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 26 -
ELECTRICAL SPECIFICATIONS
(continued)
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, Telcordia GR-499 CORE(I)
and GR-253-CORE, and ANSI T1.102-1993 for all supported rates. Transmit output jitter is guaranteed only if a
clean SONET quality transmit clock source is used.
Transmitter
Output
Jitter
Detector
Measured Jitter
Amplitude
f1
f2
20dB/decade
PARAMETER CONDITION
MIN
NOM
MAX
UNIT
10 Hz to 800 kHz
0.15
UIpp
Transmitter Output Jitter
10 kHz to 800 kHz
0.08
UIpp
Note: Filters defined by standards are used for all testing
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 27 -
ELECTRICAL SPECIFICATIONS
(continued)
TRANSMIT MONITOR
The transmit monitor function looks at the signals on the LOUTPx and LOUTNx pins and checks for the
existence of a valid signal. The monitor detects the peak of the transmitted signal at the LOUTPx and LOUTNx
pins and checks that it is between V
UNDER
and V
OVER
at all times. If the peak level is within the voltage threshold
window, the TXNW signal is low. If the peak level falls outside of the threshold limits for more than
approximately 32 bit times, the TXNW signal goes high.
V
TPOS
- V
TNEG
V
PEAK
V
OVER
V
UNDER
Time
PARAMETER CONDITION
MIN
TYP
MAX
UNIT
V
UNDER
DS3 mode with LBOx=1
STS-1 mode
320 mVpk
V
UNDER
E3 mode
DS3 mode with LBOx=0
400 mVpk
V
OVER
DS3 mode with LBOx=1
STS-1 mode
1280 mVpk
V
OVER
E3 mode
DS3 mode with LBOx=0
1600 mVpk
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 28 -
ELECTRICAL SPECIFICATIONS
(continued)
DS3/STS-1 RECEIVER (Transformer-coupled)
PARAMETER CONDITION
MIN
TYP
MAX
UNIT
MON=0.
Signal at DSX is 360-850 mVpk.
See Notes 2, 3
90 850
mVpk
MON=1 25
80
mVpk
Peak Differential Input
Amplitude, LINPx and LINNx
MON=0.
DS3-HIGH
90
1200
mVpk
Flat-loss Tolerance
MON=0.
All valid cable lengths.
0 6
dB
Receive Clock Jitter
DS3 mode with 10 Hz 400 kHz
a) Normal receive mode
b) Remote
loopback
mode
0.1
0.06
UIpp
UIpp
Interfering Tone Tolerance
(see Note 5)
Maximum ratio of Interference Power
to Signal Power for BER < 10
-8
a) With 0ft cable from DSX
b) With 450ft cable from DSX
-9
-10
dB
dB
Note 1: Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSI-
T102.1993 Figure 5. Loss characteristics of the WE728A or RG59B cable should be better than Figure
C2 of ANSI-T102.1993.
Note 2: Min spec corresponds to minimum DSX amplitude, 5.5dB of cable loss (450ft) and 6dB of flat
attenuation. Error-free receiver performance is guaranteed for up to 600ft of cable from DSX cross-
connect. Typical part can handle up to 900ft.
Note 3: Min spec corresponds to amplitude of 425mVpk at DSX, 5.5dB of cable loss (450ft) and 20dB of flat
attenuation. In monitor mode, interfering tone performance is not guaranteed.
Note 4: In this mode, no noise, jitter, or interfering tone impairments should be added for guaranteed receiver
performance.
Note 5: Interfering signal is a non-synchronous sinusoidal tone of 22.368MHz for DS3 or 25.92MHz for STS-1.
Data is a PRBS15 (2
15
-1) pattern.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 29 -
ELECTRICAL SPECIFICATIONS
(continued)
E3 RECEIVER (Transformer-coupled)
PARAMETER CONDITION
MIN
TYP
MAX
UNIT
MON=0
(See Note 1)
120 1200
mVpk
Peak Differential Input
Amplitude, LINPx and LINNx MON=1
(See Note 2)
25 100
mVpk
Flat-loss Tolerance
MON=0.
All valid cable lengths.
0 6 dB
Receive Clock Jitter
With 100Hz-800kHz filter:
a) Normal receive mode
b) Remote
loopback
mode
0.1
0.06
UIpp
UIpp
Interfering Tone Tolerance
(see Note 3)
Maximum ratio of Interference Power
to Signal Power for BER < 10
-8
a) With 0ft cable
b) With 900ft cable
-9
-10
dB
dB
Note 1: Min spec corresponds to signal amplitude of 950mVpk at source, 12dB of cable loss (1100ft) and 6dB
of flat attenuation. Error-free receiver performance is guaranteed for all cable less than 1100ft. Typical
part can handle up to 1350ft.
Note 2: Min spec corresponds to signal amplitude of 1000mVpk at source, 12dB of cable loss (1100ft) and
20dB of flat attenuation. In monitor mode, interfering tone performance is not guaranteed.
Note 3: Interfering signal is a non-synchronous E3 signal of the specified power level below the desired E3
signal. Both data and interfering signals are PRBS23 (2
23
-1) pattern.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 30 -
ELECTRICAL SPECIFICATIONS
(continued)
RECEIVER JITTER TOLERANCE
The 78P2343JAT receive jitter tolerance exceeds all specifications as shown on the graph below.
PARAMETER CONDITION MIN
NOM
MAX
UNIT
Receiver High Frequency Jitter
Tolerance
> 60 kHz
0.75
UIpp
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
10
1
10
2
10
3
10
4
10
5
10
6
10
7
Jitter Tolerance: 78P234x vs. Standards
78P234x
CORE(I) [DS3]
CORE(II) [DS3]
CORE(II) [STS1]
Jitter Frequency (Hz)
JAT enabled
GR-253-
ITU-T G.823 [E3]
ITU-T G.824 [DS3]
GR-499-
GR-499-
Jitter T
o
l
e
rance (UIp-p)
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 31 -
ELECTRICAL SPECIFICATIONS
(continued)
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop characteristics are such that the receiver has the following transfer function.
When the Jitter Attenuator (JAT) is enabled in the receive or transmit path, the receiver or transmitter will
exhibit a jitter transfer as shown in the graph and table below. Jitter Attenuator operation is guaranteed through
digital scan testing. The actual jitter transfer is guaranteed by logic design and is not tested during production
testing.
PARAMETER CONDITION MIN
NOM
MAX
UNIT
Receiver Jitter transfer function
Below Fc
0.1
dB
Receiver Jitter Bandwidth, Fc
At 3dB point
JABW= 0, E3 mode (default)
JABW= 1, E3 mode
JABW= 0, DS3 mode (default)
JABW= 1, DS3 mode
JABW= 0, STS1 mode
JABW= 1, STS1 mode (default)
JAEN= 0, JAT disabled
13
188
17
245
20
283
55
Hz
Jitter transfer function roll-off
After Fc
20
dB
per
decade
-50
-40
-30
-20
-10
0
10
Jitter Frequency
Jit
t
er Tr
ans
f
er
(dB)
10
100
1k
10k
100k
1M
ETSI TBR 24 (E3)
G
R
-25
3 C
at
I (D
S3
)
E3 JAT
DS3 JAT
STS1 JAT
JAT Disabled
G
R
-49
9 C
at
I (D
S3
)
G
R
-25
3 C
at
II (
ST
S1
)
G
R
-49
9 C
at
II (
D
S3
)
40Hz
1kHz
27Hz
40kHz
59.6kHz
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 32 -
APPLICATION INFORMATION
EXTERNAL COMPONENTS:
COMPONENT PIN(S)
VALUE
UNITS
TOLERANCE
Receiver Termination Resistor
LINPx
LINNx
84.5
1%
Transmitter Termination Resistor
LOUTPx
LOUTNx
402
1%
TRANSFORMER SPECIFICATIONS:
COMPONENT VALUE
UNITS
TOLERANCE
Turns Ratio for the Receiver
1:1
Turns Ratio for the Transmitter (center-tapped)
1:2CT
Suggested Manufacturer: Pulse, TDK, Halo
THERMAL INFORMATION
PACKAGE CONDITIONS
ja
( C/W)
Standard 100-pin JEDEC LQFP (78P2343JAT-IGT)
46
Exposed Pad 100-pin JEDEC LQFP (78P2343JAT-IEL)
No forced air,
Die attach pad soldered to PCB
24.8
SCHEMATICS
For the latest typical application schematics, please check TDK Semiconductor's website or contact your local
sales representative for the latest application note(s) and/or demo board manuals.
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 33 -
MECHANICAL SPECIFICATIONS
(Top View)
15.7 (0.618)
16.3 (0.641)
PIN No. 1
Indicator
+
15.7 (0.618)
16.3 (0.641)
13.8 (0.543) SQ
14.2 (0.559)
1.40 (0.055)
1.60 (0.063)
0.00(0)
0.20 (0.008)
0.60 (0.024) TYP.
0.50 TYP.
(0.0197)
0.18( 0.007)
0.27 (0.011)
78P2343JAT-IGT Mechanical Specification
100-pin TQFP (JEDEC LQFP)
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 34 -
MECHANICAL SPECIFICATIONS
(Bottom View)
MAX. 1.600
0.500
14.000 +/- 0.100
0.220 +/- 0.050
0.600 +/- 0.150
1.400 +/- 0.050
0.100 +/- 0.050
16.000 +/- 0.200
10.000 MAX.
10.
000
M
A
X
.
MAX.
EXPOSED
PAD AREA
16
.
0
0
0
+
/
-
0.
2
0
0
100
1
78P2343JAT-IEL Mechanical Specification
100-pin Exposed Pad LQFP (JEDEC LQFP)
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 35 -
PACKAGE INFORMATION
Pin-Out
(Top View)
78P2343JAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
63
62
61
60
59
58
57
56
55
54
53
52
51
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
LI
N
P
3
GN
D
L
O
UT
N1
LOU
T
P
1
GN
D
LI
N
P
1
LI
N
N
1
GN
D
L
O
UT
N2
LOU
T
P
2
GN
D
LI
N
P
2
LI
N
N
2
N/
C
GND
L
OUT
N3
L
OUT
P
3
GN
D
LI
N
N
3
N/
C
N/
C
GND
N/
C
N/
C
GN
D
TP
O
S
3
N/
C
N/
C
N/
C
VC
C
D
RPO
S
3
RN
E
G
3
RC
L
K
3
GNDD
TC
L
K
3
TNE
G
3
VC
C
D
RN
E
G
2
RPO
S
2
RC
L
K
2
GNDD
TC
L
K
2
TNE
G
2
TP
O
S
2
VC
C
D
RPO
S
1
RN
E
G
1
RC
L
K
1
GNDD
GNDD
VCC
VCC
VCC
VCC
VCCD
GNDD
GNDD
TPOS1
TNEG1
TCLK1
LBO1
LBO2
LBO3
N/C
VCCD
LPBK1
LPBK2
LPBK3
N/C
GND
VCC
MSL0
MSL1
ENDEC
POR
INTR2
INTR1
INTR3
N/C
SDO
N/C
N/C
VCC
VCC
VCC
VCC
GND
VCC
VCCD
SDI
SCK
CS
VCCD
VCCD
N/C
N/C
N/C
GNDD
GNDD
CKREF
100-pin TQFP (JEDEC LQFP)
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
100-pin JEDEC LQFP
78P2343JAT-IGT 78P2343JAT-IGT
100-pin JEDEC LQFP,
No Jitter Attenuator
78P2343-IGT 78P2343-IGT
100-pin JEDEC LQFP w/ Exposed Solder Pad
78P2343JAT-IEL 78P2343JAT-IEL
100-pin JEDEC LQFP w/ Exposed Solder Pad,
No Jitter Attenuator
78P2343-IEL 78P2343-IEL
Tape & Reel option
append
`R'
n/a
Lead-free option
append
`/F'
append
`/F
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
- 36 -
REVISION HISTORY
Revision Date:
Revision Description:
June 24, 2002
!
ENDEC pin addition (pin 15) and default change to ENDEC bit
!
Changed LBOx pin functionality by adding TXEN & PDTX control
!
Corrected LPBKx pin description and Intrinsic Transmit Jitter spec.
July 10, 2003
Changed to Preliminary Status
!
Added Exposed Pad package option (-IEL) and Lead-free option (/ F)
!
Updated Receive Jitter Tolerance and Jitter Transfer graphs
!
Removed SGHI bit definition
!
Updated Internal Power on Reset description
!
Added pin type CIT
!
Updated timing diagrams & e-spec table values
!
Changed recommended Rx / Tx termination resistor values to 84.5 / 402 ohm respectively
!
Added Thermal Information section
Preliminary Data Sheet:
This Preliminary Data Sheet describes a product not completely released to production. The specifications are
based on preliminary evaluations and may not be accurate. Samples of the described product are available and limited quantities can be
purchased. TDK Semiconductor Corporation should be consulted contacted for contacted to obtain the most current up-to-date information
about the product.
If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TDK Semiconductor Corporation
(TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a
data sheet is current before placing orders. TSC assumes no liability for applications assistance.
TDK Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com
2003 TDK Semiconductor Corporation
07/10/03 rev 1.7
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