SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Operates From 1.65 V to 3.6 V
D
Max t
pd
of 4.8 ns at 3.3 V
D
24 mA Output Drive at 3.3 V
D
B-Port Outputs Have Equivalent 26-
Series Resistors, So No External Resistors
Are Required
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
description/ordering information
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH162268 is used for applications
in which data must be transferred from a narrow
high-speed bus to a wide, lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input when the appropriate
clock-enable (CLKEN) inputs are low. The select
(SEL) line is synchronous with CLK and selects
1B or 2B input data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single
storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be
presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74ALVCH162268DL
ALVCH162268
SSOP - DL
Tape and reel
SN74ALVCH162268DLR
ALVCH162268
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74ALVCH162268GR
ALVCH162268
-40 C to 85 C
VFGBA - GQL
Tape and reel
SN74ALVCH162268KR
VH2268
VFGBA - ZQL (Pb-free)
Tape and reel
74ALVCH162268ZQLR
VH2268
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEA
CLKEN1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
CLKEN2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Widebus is a trademark of Texas Instruments.
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-
resistors to reduce overshoot
and undershoot.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible, and OE should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
terminal assignments
1
2
3
4
5
6
A
2B3
CLKEN1B
OEA
OEB
CLKENA2
2B4
B
2B1
2B2
GND
GND
2B5
2B6
C
A2
A1
VCC
VCC
2B7
2B8
D
A4
A3
GND
GND
2B9
2B10
E
A6
A5
2B11
2B12
F
A7
A8
1B11
1B12
G
A9
A10
GND
GND
1B9
1B10
H
A11
A12
VCC
VCC
1B7
1B8
J
1B1
1B2
GND
GND
1B5
1B6
K
1B3
CLKEN2B
SEL
CLK
CLKENA1
1B4
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
K
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Function Tables
OUTPUT ENABLE
INPUTS
OUTPUTS
CLK
OEA
OEB
A
1B, 2B
H
H
Z
Z
H
L
Z
Active
L
H
Active
Z
L
L
Active
Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
A
1B
2B
H
H
X
X
1B0
2B0
L
L
L
L
X
L
L
H
H
X
X
L
L
X
L
X
L
H
X
H
Output level before the indicated steady-state input
conditions were established
Two CLK edges are needed to propagate data
B-TO-A STORAGE (OEA = L)
INPUTS
OUTPUT
CLKEN1B
CLKEN2B
CLK
SEL
1B
2B
OUTPUT
A
H
X
X
H
X
X
A0
X
H
X
L
X
X
A0
L
L
H
L
X
L
L
L
H
H
X
H
X
L
L
X
L
L
X
L
L
X
H
H
Output level before the indicated steady-state input conditions were
established
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
CLK
OEB
SEL
A1
1B1
2B1
CLKENA1
CLKENA2
1D
1D
CE
C1
1D
CE
C1
G1
1
1
1D
1D
CLKEN1B
C1
1D
1D
C1
CE
OEA
1D
C1
C1
CLKEN2B
1 of 12 Channels
CE
CE
C1
2
27
30
55
56
28
1
29
8
23
6
C1
1D
Pin numbers shown are for the DGG and DL packages.
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1)
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
56
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL/ZQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
0.65
VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
2
V
VCC = 1.65 V to 1.95 V
0.35
VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
-4
High-level output current (A port)
VCC = 2.3 V
-12
High-level output current (A port)
VCC = 2.7 V
-12
IOH
VCC = 3 V
-24
mA
IOH
VCC = 1.65 V
-2
mA
High-level output current (B port)
VCC = 2.3 V
-6
High-level output current (B port)
VCC = 2.7 V
-8
VCC = 3 V
-12
VCC = 1.65 V
4
Low-level output current (A port)
VCC = 2.3 V
12
Low-level output current (A port)
VCC = 2.7 V
12
IOL
VCC = 3 V
24
mA
IOL
VCC = 1.65 V
2
mA
Low-level output current (B port)
VCC = 2.3 V
6
Low-level output current (B port)
VCC = 2.7 V
8
VCC = 3 V
12
t/
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = -100
A
1.65 V to 3.6 V
VCC-0.2
IOH = -4 mA
1.65 V
1.2
IOH = -6 mA
2.3 V
2
A port
2.3 V
1.7
A port
IOH = -12 mA
2.7 V
2.2
IOH = -12 mA
3 V
2.4
VOH
IOH = -24 mA
3 V
2
V
VOH
IOH = -100
A
1.65 V to 3.6 V
VCC-0.2
V
IOH = -2 mA
1.65 V
1.2
IOH = -4 mA
2.3 V
1.9
B port
IOH = -6 mA
2.3 V
1.7
B port
IOH = -6 mA
3 V
2.4
IOH = -8 mA
2.7 V
2
IOH = -12 mA
3 V
2
IOL = 100
A
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
A port
IOL = 6 mA
2.3 V
0.4
A port
IOL = 12 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3 V
0.55
VOL
IOL = 100
A
1.65 V to 3.6 V
0.2
V
VOL
IOL = 2 mA
1.65 V
0.45
V
IOL = 4 mA
2.3 V
0.4
B port
IOL = 6 mA
2.3 V
0.55
B port
IOL = 6 mA
3 V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3 V
0.8
II
VI = VCC or GND
3.6 V
5
A
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
II(hold)
VI = 1.7 V
2.3 V
-45
A
II(hold)
VI = 0.8 V
3 V
75
A
VI = 2 V
3 V
-75
VI = 0 to 3.6 V
3.6 V
500
IOZ
VO = VCC or GND
3.6 V
10
A
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
A
ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
750
A
Ci
Control inputs
VI = VCC or GND
3.3 V
3.5
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
9
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
For I/O ports, the parameter IOZ includes the input leakage current.
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
0.2 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
120
125
150
MHz
tw
Pulse duration, CLK high or low
3.3
3.3
3.3
ns
A data before CLK
4.5
4
3.4
B data before CLK
0.8
1.2
1
tsu
Setup time
SEL before CLK
1.4
1.6
1.3
ns
tsu
Setup time
CLKENA1 or CLKENA2 before CLK
3.6
3.4
2.8
ns
CLKEN1B or CLKEN2B before CLK
3.2
3
2.5
OE before CLK
4.2
3.9
3.2
A data after CLK
0
0
0.2
B data after CLK
1.3
1.2
1.3
th
Hold time
SEL after CLK
1
1
1
ns
th
Hold time
CLKENA1 or CLKENA2 after CLK
0.1
0.1
0.4
ns
CLKEN1B or CLKEN2B after CLK
0.1
0
0.5
OE after CLK
after CLK
0
0
0.2
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
VCC = 2.5 V
0.2 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
120
125
150
MHz
B
8
1.6
6.1
5.9
1.8
5.4
tpd
CLK
A (1B)
8
1.6
5.8
5.4
1.7
4.8
ns
tpd
CLK
A (2B)
8
1.6
5.8
5.3
1.8
4.8
ns
A (SEL)
11
2.5
7.3
6.5
2.4
5.8
ten
CLK
B
12
2.7
7.2
6.8
2.6
6.1
ns
tdis
CLK
B
10
2.8
7.2
6.1
2.5
5.9
ns
ten
CLK
A
9
2
6.2
5.6
1.8
5.1
ns
tdis
CLK
A
9
2
6.5
5.4
2.1
5
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
UNIT
Cpd
Power dissipation capacitance
Outputs enabled
CL = 50 pF,
f = 10 MHz
87
120
pF
Cpd
Power dissipation capacitance
Outputs disabled
CL = 50 pF,
f = 10 MHz
80.5
118
pF
SN74ALVCH162268
12 BIT TO 24 BIT REGISTERED BUS EXCHANGER
WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V
VOH - V
0 V
VI
0 V
0 V
tw
VI
VI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VM
VM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
VM
tPLH
VLOAD
VLOAD/2
1.8 V
0.15 V
2.5
0.2 V
2.7 V
3.3 V
0.3 V
1 k
500
500
500
VCC
RL
2
VCC
2
VCC
6 V
6 V
VLOAD
CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUT
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2003, Texas Instruments Incorporated
PDF 
ZIP